ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
Figure 29. Lite timer block diagram
fLTIMER To 12-bit auto-reload tImer
fOSC
13-bit upcounter
fWDG
/2
fLTIMER
1
Timebase
0
1 or 2 ms
(@ 8 MHz
fOSC)
Watchdog
Watchdog reset
LTICR
8 MSB
) - Obsolleettee PPrroodduucctt((ss)) LTIC
8-bit
input capture
register
LTCSR
ICIE ICF
WDG
TB TBIE TBF RF WDGE WDGD
7
0
LTTB interrupt request
LTIC interrupt request
ct(s bso 10.1.3 Functional description
du - O The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts
ro ) incrementing from 0 at a frequency of fOSC. A counter overflow event occurs when the counter rolls over
P t(s from 1F39h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1ms.
te c This period can be doubled by setting the TB bit in the LTCSR register.
le du When the timer overflows, the TBF bit is set by hardware and an interrupt request is generated if the
so ro TBIE is set. The TBF bit is cleared by software reading the LTCSR register.
b P Watchdog
O lete The watchdog is enabled using the WDGE bit. The normal watchdog timeout is 2ms (@ fOSC = 8 MHz),
after which it then generates a reset.
so To prevent this watchdog reset from occurring, software must set the WDGD bit. The WDGD bit is
Obcleared by hardware after tWDG. This means that software must write to the WDGD bit at regular intervals
to prevent a watchdog reset from occurring. Refer to Figure 38.
If the watchdog is not enabled immediately after reset, the first watchdog timeout will be shorter than
2ms, because this period is counted starting from reset. Moreover, if a 2ms period has already elapsed
after the last MCU reset, the watchdog reset will take place as soon as the WDGE bit is set. For these
reasons, it is recommended to enable the watchdog immediately after reset or else to set the WDGD bit
before the WGDE bit so a watchdog reset will not occur for at least 2ms.
64/124
Share Link: 