ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
ST7LUS5, ST7LU05, ST7LU09
On-chip peripherals
10.1.6
Register description
Lite timer control/status register (LTCSR)
LTCSR
Reset value: 0000 0x00 (0xh)
7
6
5
4
3
2
1
0
ICIE
ICF
TB
TBIE
TBF
WDGRF WDGE WDGD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 35. LTCSR register description
Bit Name
Function
t(s) Interrupt enable
uc 7 ICIE
This bit is set and cleared by software.
0: Input capture (IC) interrupt disabled
1: Input capture (IC) interrupt enabled
rod ) Input capture flag
P t(s This bit is set by hardware and cleared by software by reading the LTICR register.
lete uc 6 ICF
Writing to this bit does not change the bit value.
0: No input capture
d 1: An input capture has occurred
so ro Note: After an MCU reset, software must initialize the ICF bit by reading the LTICR
register.
- Ob te P Timebase period selection
t(s) sole 5
TB
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8 MHz)
c b Timebase interrupt enable
rodu ) - O 4 TBIE
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
P t(s Timebase interrupt flag
solete roduc 3 TBF
This bit is set by hardware and cleared by software reading the LTCSR register.
Writing to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
b P Force reset/reset status flag
OObsolete2 WDGRF
This bit is used in two ways: It is set by software to force a watchdog reset. It is set
by hardware when a watchdog reset occurs and cleared by hardware or by
software. It is cleared by hardware only when an LVD reset occurs. It can be
cleared by software after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog reset occurred (read).
67/124
Share Link: 