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ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST7FLU05MCE' PDF : 124 Pages View PDF
ST7LUS5, ST7LU05, ST7LU09
On-chip peripherals
10.2 12-bit autoreload timer
10.2.1
Introduction
The 12-bit autoreload timer can be used for general-purpose timing functions. It is based on
a free-running 12-bit upcounter with a PWM output channel.
10.2.2 Main features
12-bit upcounter with 12-bit autoreload register (ATR)
Maskable overflow interrupt
PWM signal generator
Frequency range 2 kHz to 4 MHz (@ 8 MHz fCPU)
t(s) – Programmable duty-cycle
– Polarity control
uc – Maskable compare interrupt
d Output compare function
Pro t(s) Figure 32. Block diagram
lete duc 7 ATCSR
so ro 0
0
OVF interrupt
0 request
0 CK1 CK0 OVF OVFIE CMPIE
) - Ob lete P fLTIMER
t(s o (1ms timebase
s @ 8 MHz)
uc Ob fCPU
te Prod ct(s) - DCR0H
le u Preload
DCR0L
Preload
bso Prodon OVF event
IF OE0=1
O te12-bit duty cycle value (shadow)
fCOUNTER
CNTR
ATR
CMPF0
CMP interrupt
request
12-bit upcounter
Update on OVF event
12-bit autoreload value
OE0 bit
OE0 bit CMPF0 bit
0
Compare
1
OP0 bit
fPWM Polarity
PWM0
Obsole 10.2.3 Functional description
PWM mode
This mode allows a pulse width modulated signals to be generated on the PWM0 output pin
with minimum core processing overhead. The PWM0 output signal can be enabled or
disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is
configured as output push-pull alternate function.
Note:
CMPF0 is available in PWM mode (see PWM0CSR register description on page 85).
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