ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
Table 35. LTCSR register description (continued)
Bit Name
Function
Watchdog enable
1 WDGE
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Watchdog reset delay
0 WDGD
This bit is set by software. It is cleared by hardware at the end of each tWDG period.
0: Watchdog reset not delayed
1: Watchdog reset delayed
Lite timer input capture register (LTICR)
t(s) LTICR
Reset value: 0000 0000 (00h)
c 7
6
5
4
3
2
1
0
du ICR[7:0]
Pro t(s) RO
te c Table 36. LTICR register description
le du Bit Name
Function
so ro Input capture value
) - Ob lete P 7:0 ICR[7:0]
These bits are read by software and cleared by hardware after a reset. If the ICF
bit in the LTCSR is cleared, the value of the 8-bit upcounter will be captured when
a rising or falling edge occurs on the LTIC pin.
t(s so Table 37. Lite timer register map and reset values
uc Ob Address
d - (Hex.)
Register
label
7
6
5
4
3
2
1
0
Pro t(s) 0B
LTCSR
ICIE ICF
Reset value 0
0
TB TBIE TBF WDGRF WDGE WDGD
0
0
0
x
0
0
OObbssoolleettee Produc 0C
LTICR
ICR7 ICR6 ICR5 ICR4 ICR3
Reset value 0
0
0
0
0
ICR2
0
ICR1 ICR0
0
0
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