ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
10.2.5 Interrupts
Table 39. Auto-reload timer interrupt control/wake-up capability
Interrupt event(1)
Event flag
Enable control
bit
Exit from
wait
Exit from
halt
Exit from
active halt
Overflow event
OVF
OVFIE
Yes
CMP event
CMPFx
CMPIE
Yes(2)
No
No
1. The interrupt events are connected to separate interrupt vectors (see Chapter 7: Interrupts).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC
register is reset (RIM instruction).
2. Only if CK0 = 1 and CK1 = 0.
ct(s) 10.2.6
Register description
Timer control status register (ATCSR)
rodu ATCSR
P t(s) 7
6
5
te c Reserved
le du -
4
3
CK[1:0]
R/W
Reset value: 0000 0000 (00h)
2
1
0
OVF
OVFIE CMPIE
R/W
R/W
R/W
bso Pro Table 40. ATCSR register description
- O te Bit Name
Function
) le 7:5
-
Reserved, must be kept cleared.
t(s so Counter clock selection
te Producct(s) - Ob 4:3 CK[1:0]
These bits are set and cleared by software and cleared by hardware after a reset.
They select the clock frequency of the counter.
00: Off
01: fLTIMER (1ms timebase @ 8 MHz)
10: fCPU
11: Reserved
le du Overflow flag
Obso te Pro 2 OVF
This bit is set by hardware and cleared by software by reading the ATCSR
register. It indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
le Caution: When set, the OVF bit stays high for 1 fCOUNTER cycle (up to 1ms
Obso depending on the clock selection) after it has been cleared by software.
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