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ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST7FLU05MCE' PDF : 124 Pages View PDF
On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
10.3.4
Note:
Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 47. Effect of low power modes on ADC
Mode
Description
Wait No effect on A/D converter
A/D converter disabled
Halt After wake-up from halt mode, the A/D converter requires a stabilization time tSTAB (see
Electrical characteristics) before accurate conversions can be performed.
) 10.3.5
Productt((ss) 10.3.6
Interrupts
None.
Register description
Control/status register (ADCCSR)
lete uc ADCCSR
so rod 7
b P EOC
- O te RO
6
SPEED
R/W
5
ADON
R/W
4
3
Reserved
-
Reset value: 0000 0000 (00h)
2
1
0
CH[2:0]
R/W
t(s) ole Table 48. ADCCSR register description
c bs Bit Name
Function
du - O End of conversion
te Pro ct(s) 7 EOC
This bit is set by hardware. It is cleared by hardware when software reads the
ADCDRH register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
le du ADC clock selection
so ro 6 SPEED This bit is set and cleared by software. It is used together with the SLOW bit to
b P configure the ADC clock speed. Refer to the table in the SLOW bit description.
O te A/D converter on
sole5 ADON
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Ob 4:3 - Reserved, must be kept cleared
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