On-chip peripherals
Figure 35. ADC block diagram
fCPU
DIV 2
0
1
DIV 4
ST7LUS5, ST7LU05, ST7LU09
1
0
SLOW
bit
fADC
EOC SPEED ADON 0
0 CH2 CH1 CH0 ADCCSR
3
) AIN0
t(s AIN1
roduc ) AINx
Analog
mux
RADC
Hold control
CADC
Analog to digital
converter
lete P uct(s ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
so rod ADCDRL
00
0 0 SLOW 0 D1 D0
) - Ob lete P Digital A/D conversion result
t(s so The conversion is monotonic, meaning that the result never decreases if the analog input
c b does not and never increases if the analog input does not.
du - O If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the
ro ) conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
P t(s overflow indication).
te c If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
le u conversion result in the ADCDRH and ADCDRL registers is 00 00h.
so rod The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
b P and ADCDRL registers. The accuracy of the conversion is described in the Chapter 12:
Electrical characteristics.
O leteRAIN is the maximum recommended impedance for an analog input signal. If the impedance
o is too high, this will result in a loss of accuracy due to leakage and sampling not being
Obs completed in the allocated time.
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