ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
ST7LUS5, ST7LU05, ST7LU09
On-chip peripherals
Table 40. ATCSR register description
Bit Name
Function
Overflow interrupt enable
1 OVFIE
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
Compare interrupt enable
0 CMPIE
This bit is read/write by software and cleared by hardware after a reset. It is used
to mask the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
Counter register high (CNTRH)
t(s) CNTRH
uc 15
14
13
12
rod ) Reserved
P t(s -
lete uc Counter register low (CNTRL)
11
CNTR11
RO
Reset value: 0000 0000 (00h)
10
9
8
CNTR10 CNTR9 CNTR8
RO
RO
RO
bso Prod CNTRL
- O te 7
) le CNTR7
t(s so RO
6
CNTR6
RO
5
CNTR5
RO
4
CNTR4
RO
3
CNTR3
RO
Reset value: 0000 0000 (00h)
2
1
0
CNTR2 CNTR1 CNTR0
RO
RO
RO
uc Ob Table 41. CNTR high and low counter descriptions
rod ) - Bits Name
Function
P t(s 15:12
-
Reserved, must be kept cleared.
lete ucCounter value
OObbssoolete Prod 11:0 CNTR[11:0]
This 12-bit register is read by software and cleared by hardware after a reset.
The counter is incremented continuously as soon as a counter clock is
selected. To obtain the 12-bit value, software should read the counter value in
two consecutive read operations. The CNTRH register can be incremented
between the two reads, and in order to be accurate when fTIMER = fCPU, the
software should take this into account when CNTRL and CNTRH are read. If
CNTRL is close to its highest value, CNTRH could be incremented before it is
read. When a counter overflow occurs, the counter restarts from the value
specified in the ATR register.
73/124
Share Link: 