ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
ST7LUS5, ST7LU05, ST7LU09
On-chip peripherals
PWM0 duty cycle register low (DCR0L)
DCR0L
7
DCR7
R/W
6
DCR6
R/W
5
DCR5
R/W
4
DCR4
R/W
3
DCR3
R/W
Reset value: 0000 0000 (00h)
2
1
0
DCR2
DCR1
DCR0
R/W
R/W
R/W
Table 43. DCR0 high and low register descriptions
Bits Name
Function
15:12
-
Reserved, must be kept cleared
) PWMx duty cycle value
t(s This 12-bit value is written by software. The high register must be written first.
roduc ) 11:0 DCR[11:0]
In PWM mode (OE0 = 1 in the PWMCR register) the DCR[11:0] bits define the
duty cycle of the PWM0 output signal (see Figure 41). In output compare
mode, (OE0 = 0 in the PWMCR register) they define the value to be compared
with the 12-bit upcounter value.
P t(s PWM0 control/status register (PWM0CSR)
lete duc PWM0CSR
Reset value: 0000 0000 (00h)
so ro 7
6
5
4
3
2
1
0
b P Reserved
OP0
CMPF0
) - O lete -
R/W
R/W
t(s so Table 44. PWM0CSR register description
uc Ob Bit Name
Function
rod - 7:2
- Reserved, must be kept cleared.
P t(s) PWM0 output polarity
te c This bit is read/write by software and cleared by hardware after a reset. This bit
le u 1
OP0 selects the polarity of the PWM0 signal.
d0: The PWM0 signal is not inverted.
so ro 1: The PWM0 signal is inverted.
b P PWM0 compare flag
O te This bit is set by hardware and cleared by software by reading the PWM0CSR
le 0 CMPF0 register. It indicates that the upcounter value matches the DCR0 register value.
0: Upcounter value does not match DCR value
Obso 1: Upcounter value matches DCR value
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