ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
On-chip peripherals
11.4.7
Interrupts
Table 41. Interrupt events
Interrupt Event
SPI end of transfer event
Master mode fault event
Overrun error
Event
flag
SPIF
MODF
OVR
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Enable
control
bit
SPIE
Exit
from
WAIT
Yes
Yes
Yes
Exit
from
HALT
Yes
No
No
Note:
11.4.8
The SPI interrupt events are connected to the same interrupt vector (see Section 8:
Interrupts).
They generate an interrupt if the corresponding Enable Control bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
Register description
Control register (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
7
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
0
SPR0
Note:
● Bit 7 = SPIE Serial peripheral interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master mode Fault
or Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register).
● Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS=0 (see Section : Master mode fault (MODF)). The SPE bit is cleared by
reset, so the SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled.
● Bit 5 = SPR2 Divider enable
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to Table 42: SPI Master mode SCK frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
This bit has no effect in slave mode.
● Bit 4 = MSTR Master mode
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS=0 (see Section : Master mode fault (MODF)).
0: Slave mode
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Doc ID 8349 Rev 5
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