ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Note:
Figure 46 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin, the MOSI pin are directly connected between the master and the slave device.
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Figure 46. Data clock timing diagram
SCK
(CPOL = 1)
SCK
(CPOL = 0)
CPHA =1
MISO
(from master)
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MOSI
(from slave)
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
SS
(to slave)
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
CPHA =0
MISO
(from master)
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MOSI
(from slave)
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
SS
(to slave)
CAPTURE STROBE
Note:
11.4.5
This figure should not be used as a replacement for parametric information. Refer to the
Section 13: Electrical characteristics.
Error Flags
Master mode fault (MODF)
Master mode fault occurs when the master device has its SS pin pulled low.
When a Master mode fault occurs:
1. The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
2. The SPE bit is reset. This blocks all output from the Device and disables the SPI
peripheral.
3. The MSTR bit is reset, thus forcing the Device into slave mode.
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Doc ID 8349 Rev 5
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