ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
On-chip peripherals
Figure 43. Single master/ single slave application
MASTER
MSBit
LSBit
8-BIT SHIFT REGISTER
MISO
MOSI
MISO
MOSI
MSBit
SLAVE
LSBit
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS +5V
SCK
SS
Not used if SS is managed
by software
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 45: Hardware/software slave select management).
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode:
SS internal must be held high continuously.
In Slave mode:
There are two cases depending on the data/clock timing relationship (see Figure 44):
1. If CPHA=1 (data latched on 2nd clock edge):
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to VSS, or made free for standard I/O by
managing the SS function by software (SSM= 1 and SSI=0 in the SPICSR register),
2. If CPHA=0 (data latched on 1st clock edge):
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write
Collision error will occur when the slave writes to the shift register (see Write collision
error (WCOL)).
Figure 44. Generic SS timing diagram
MOSI/MISO
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Byte 1
Byte 2
Byte 3
Doc ID 8349 Rev 5
93/166
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