ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Figure 42. Serial peripheral interface block diagram
SPIDR
Data/Address Bus
Read
Read Buffer
Interrupt
request
MOSI
MISO
SOD
bit
SCK
8-Bit Shift Register
Write
7
SPIF WCOL OVR MODF 0
SPICSR 0
SOD SSM SSI
SPI
STATE
CONTROL
SS 1
0
7
SPICR 0
MASTER
CONTROL
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
SERIAL CLOCK
GENERATOR
SS
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 43: Single master/ single slave application.
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 46: Data clock
timing diagram) but master and slave must be programmed with the same timing mode.
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Doc ID 8349 Rev 5
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