TDA7503
MAXIMUM DSP CLOCK FREQUENCY (Fdsp) VERSUS JUNCTION TEMPERATURE (Tj)
MHz
MHz
63
61
57
55
48
46
˚C
˚C
-40
25
125
-40
25
125
@3.3V
@3.15V
MHz
66
59
49
-40
˚C
25
125
@3.45V
D02AU1421
SAI/SSI INTERFACE
Timing
Description
tsckr Minimum Clock Cycle
tdt SCKR active edge to data out valid
tlrs LRCK setup time
tlrh LRCK hold time
tsdid SDI setup time
tsdih SDI hold time
tsckph Minimum SCK high time
tsckpl Minimum SCK low time
Note TDSP = dsp master clock cycle time = 1/FDSP
Value
3TDSP+5
40
5
5
5
5
0.35 tsckr
0.35 tsckr
Unit
ns
ns
ns
ns
ns
ns
ns
ns
12/30