TDA7503 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7503' PDF : 30 Pages View PDF
TDA7503
SP INTERFACE
Symbol
tsclk
Clock Cycle
tdtr
Sclk edge to MOSI valid
tdts
MISO setup time
tsclk
tdtr
tdts
tsckph
tsckpl
Clock Cycle
Sclk edge to MOSI valid
MISO setup time
Minimum SCK high time
Minimum SCK low time
Description
MASTER
SLAVE
Figure 8. SPI Clocking scheme
SS
Min Value
mclk/12
40
5
mclk/6
40
5
mclk/12
mclk/12
Unit
µs
µs
µs
µs
µs
µs
µs
µs
SCLK
(CPOL=0, CPHA=0)
SCLK
(CPOL=0, CPHA=1)
SCLK
(CPOL=1, CPHA=0)
SCLK
(CPOL=1, CPHA=1)
MISO, MOSI
MSB
6
5
4
3
2
1
LSB
INTERNAL STROBE FOR DATA CAPTURE
D02AU1378
MICRO MEMORY INTERFACE
For the calculation of slowest access time allowed for a memory attached to the MX51, the following diagram
illustrates the timing constraints. Slowest access time allowed, tacc = 4*mclk - tad - tds, where the worst case
address delay, tad = 30 ns, and the worst case data setup time, tds = 20 ns.
Figure 9. Timing diagram for External Memory Interface
mclk
XALE
XPSEN
OPLOAD
ADDRESS
DATA
D02AU1379
tad
tacc
tds
16/30
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