TDA7503 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7503' PDF : 30 Pages View PDF
Figure 7. SSI Protocol
FRAME
SYNC 0
FRAME
SYNC 1
DATA IN
SCK
RECEIVE
INTERRUPTS
FRAME
SYNC 0
FRAME
SYNC 1
DATA IN
SCK
RECEIVE
INTERRUPTS
FIVE WORD PACKET
NETWORK MODE
DATA WORD
NORMAL MODE
TDA7503
D02AU1377
The timing diagrams for the SSI Interface are shown in Figure 7 for both Network and Normal modes.
In Normal Mode the rising edge FSYNC starts the internal bit counter to allow data to be clocked in or out. When
bit count is equal to the programmed word length the counter is reset and the shift register is broadside loaded
into the data register. Additional SCK pulses are ignored after the counter is reset. The next word is clocked in
or out starting with the next rising edge of FSYNC.
In Network Mode the rising edge FSYNC starts the internal bit counter to allow data to be clocked in or out.
When bit count is equal to the programmed word length the counter is reset and the shift register is broadside
loaded into the data register. At this point the FSRSD bit is set indicating that a frame sync was received with
that word. After being reset the counter continues counting, clocking in the next word. Only when the next rising
edge of FSYNC is detected is the packet considered complete.
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