XRT79L71IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71IB' PDF : 441 Pages View PDF
PRELIMINARY
XRT79L71
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
FIGURE 4. THE FUNCTIONAL BLOCK DIAGRAM OF THE XRT79L71 WHEN IT HAS BEEN CONFIGURED TO OPERATE IN THE ATM UNI OVER
DS3/E3 MODE ............................................................................................................................................................... 14
1.3.1 THE TRANSMIT UTOPIA INTERFACE BLOCK ........................................................................................................ 15
1.3.2 THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK (NOT SHOWN IN Figure 4).......................... 15
1.3.3 THE TRANSMIT FEAC CONTROLLER BLOCK (DS3, C-BIT PARITY APPLICATIONS ONLY)............................. 15
1.3.4 THE TRANSMIT TRAIL-TRACE MESSAGE CONTROLLER BLOCK (E3, ITU-T G.832 APPLICATIONS ONLY).. 15
1.3.5 THE TRANSMIT SSM CONTROLLER BLOCK (E3, ITU-T G.832 APPLICATIONS ONLY) ..................................... 15
1.3.6 THE TRANSMIT LAPD CONTROLLER BLOCK........................................................................................................ 16
1.3.7 THE TRANSMIT PLCP PROCESSOR BLOCK (CAN BE BY-PASSED)................................................................... 16
1.3.8 THE TRANSMIT DS3/E3 FRAMER BLOCK............................................................................................................... 16
1.3.9 THE TRANSMIT DS3/E3 LIU BLOCK ........................................................................................................................ 17
1.3.10 THE RECEIVE DS3/E3 LIU BLOCK ......................................................................................................................... 17
1.3.11 THE RECEIVE DS3/E3 FRAMER BLOCK ............................................................................................................... 17
1.3.12 THE RECEIVE PLCP PROCESSOR BLOCK (CAN BE BY-PASSED) ................................................................... 17
1.3.13 THE RECEIVE LAPD CONTROLLER BLOCK ........................................................................................................ 18
1.3.14 THE RECEIVE SSM CONTROLLER BLOCK (E3, ITU-T G.832 APPLICATIONS ONLY)...................................... 18
1.3.15 THE RECEIVE TRAIL-TRACE MESSAGE CONTROLLER BLOCK (E3, ITU-T G.832 APPLICATIONS ONLY) .. 18
1.3.16 THE RECEIVE FEAC CONTROLLER BLOCK (DS3, C-BIT PARITY APPLICATIONS ONLY) ............................. 18
1.3.17 THE RECEIVE ATM CELL PROCESSOR BLOCK .................................................................................................. 18
1.3.18 THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK ....................................................................... 18
1.3.19 THE RECEIVE UTOPIA INTERFACE BLOCK ......................................................................................................... 18
1.3.20 A MORE DETAILED FUNCTIONAL/ARCHITECTURAL DESCRIPTION OF THE XRT79L71, WHEN CONFIGURED TO
OPERATE IN THE ATM UNI MODE, CAN BE FOUND IN THE DOCUMENT (79L71_ARCH_DESCR_ATM.PDF). .. 19
1.4 FUNCTIONAL ARCHITECTURE/DESCRIPTION OF THE XRT79L71 - PPP OVER DS3/E3 MODE ........... 19
FIGURE 5. THE FUNCTIONAL BLOCK DIAGRAM OF THE XRT79L71 WHEN IT HAS BEEN CONFIGURED TO OPERATE IN THE PPP OVER DS3/
E3 MODE ....................................................................................................................................................................... 19
1.4.1 THE TRANSMIT POS-PHY INTERFACE BLOCK...................................................................................................... 20
1.4.2 THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK........................................................................... 20
1.4.3 THE TRANSMIT PPP PACKET PROCESSOR BLOCK ............................................................................................ 20
1.4.4 THE TRANSMIT FEAC CONTROLLER BLOCK (DS3, C-BIT PARITY APPLICATIONS ONLY)............................. 20
1.4.5 THE TRANSMIT TRAIL-TRACE MESSAGE CONTROLLER BLOCK (E3, ITU-T G.832 APPLICATIONS ONLY).. 21
1.4.6 THE TRANSMIT SSM CONTROLLER BLOCK (E3, ITU-T G.832 APPLICATIONS ONLY) ..................................... 21
1.4.7 THE TRANSMIT LAPD CONTROLLER BLOCK........................................................................................................ 21
1.4.8 THE TRANSMIT DS3/E3 FRAMER BLOCK............................................................................................................... 21
1.4.9 THE TRANSMIT DS3/E3 LIU BLOCK ........................................................................................................................ 21
1.4.10 THE RECEIVE DS3/E3 LIU BLOCK ......................................................................................................................... 21
1.4.11 THE RECEIVE DS3/E3 FRAMER BLOCK ............................................................................................................... 22
1.4.12 THE RECEIVE LAPD CONTROLLER BLOCK ........................................................................................................ 22
1.4.13 THE RECEIVE SSM CONTROLLER BLOCK (E3, ITU-T G.832 APPLICATIONS ONLY)...................................... 22
1.4.14 THE RECEIVE TRAIL-TRACE MESSAGE CONTROLLER BLOCK (E3, ITU-T G.832 APPLICATIONS ONLY) .. 22
1.4.15 THE RECEIVE FEAC CONTROLLER BLOCK (DS3, C-BIT PARITY APPLICATIONS ONLY) ............................. 23
1.4.16 THE RECEIVE PPP PACKET PROCESSOR BLOCK ............................................................................................. 23
1.4.17 THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK ....................................................................... 23
1.4.18 THE RECEIVE POS-PHY INTERFACE BLOCK ...................................................................................................... 23
1.4.19 A MORE DETAILED FUNCTIONAL/ARCHITECTURAL DESCRIPTION OF THE XRT79L71, WHEN CONFIGURED TO
OPERATE IN THE PPP MODE CAN BE FOUND IN THE DOCUMENT (79L71_ARCH_DESCR_PPP.PDF)............. 23
2.0 MICROPROCESSOR INTERFACE ..................................................................................................... 23
TABLE 3: LIST AND BRIEF DESCRIPTION OF THE MICROPROCESSOR INTERFACE PINS ...................................................................... 24
2.1 OPERATING THE MICROPROCESSOR INTERFACE IN THE INTEL-ASYNCHRONOUS MODE ............. 30
TABLE 4: THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE INTEL-ASYNCHRONOUS
MODE ............................................................................................................................................................................ 31
2.1.1 THE INTEL-ASYNCHRONOUS READ-CYCLE.......................................................................................................... 32
FIGURE 6. BEHAVIOR OF MICROPROCESSOR INTERFACE SIGNALS DURING AN "INTEL-ASYNCHRONOUS" READ OPERATION. ............... 33
2.1.2 THE INTEL-ASYNCHRONOUS WRITE CYCLE ........................................................................................................ 33
FIGURE 7. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING AN "INTEL-ASYNCHRONOUS" WRITE OPERATION. ..... 34
2.2 OPERATING THE MICROPROCESSOR INTERFACE IN THE MOTOROLA-ASYNCHRONOUS MODE ... 35
TABLE 5: THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE MOTOROLA-ASYNCHRO-
NOUS MODE ................................................................................................................................................................... 35
2.2.1 THE MOTOROLA-ASYNCHRONOUS READ-CYCLE ............................................................................................... 36
FIGURE 8. ILLUSTRATION OF THE BEHAVIOR OF MICROPROCESSOR INTERFACE SIGNALS, DURING A "MOTOROLA-ASYNCHRONOUS" READ
OPERATION. ................................................................................................................................................................... 37
2.2.2 THE MOTOROLA-ASYNCHRONOUS WRITE-CYCLE.............................................................................................. 37
FIGURE 9. ILLUSTRATION OF THE BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNAL, DURING A "MOTOROLA-ASYNCHRONOUS" WRITE
OPERATION. ................................................................................................................................................................... 38
2.3 OPERATING THE MICROPROCESSOR INTERFACE IN THE POWERPC 403 MODE .............................. 38
TABLE 6: THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE POWERPC 403 MODE
II
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