XRT79L71IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71IB' PDF : 441 Pages View PDF
PRELIMINARY
XRT79L71
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
TABLE 14: A SUMMARY OF THE "TRANSMIT PAYLOAD DATA INPUT INTERFACE" MODES ................................................................... 73
4.2.1.1 MODE 1 - SERIAL/LOOP-TIMING MODE OPERATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ... 73
FIGURE 30. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT PAYLOAD DATA INPUT
INTERFACE BLOCK OF THE XRT79L71 FOR MODE 1 (SERIAL/LOOP-TIMING) OPERATION .................................................. 74
FIGURE 31. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 1 (SERIAL/LOOP-TIMING)
MODE OPERATION.......................................................................................................................................................... 75
4.2.1.2 MODE 2 - SERIAL/LOCAL-TIMING/FRAME SLAVE MODE OPERATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK ..................................................................................................................................................................... 76
FIGURE 32. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 2 (SERIAL/LOCAL-TIM-
ING/FRAME-SLAVE) MODE OPERATION ............................................................................................................................ 76
FIGURE 33. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 2 (SERIAL/LOCAL-TIM-
ING/FRAME-SLAVE) MODE OPERATION ............................................................................................................................ 78
4.2.1.3 MODE 3 - SERIAL/LOCAL-TIMING/FRAME MASTER MODE OPERATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK ..................................................................................................................................................................... 78
FIGURE 34. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 3 (SERIAL/LOCAL-TIM-
ING/FRAME-SLAVE) MODE OPERATION ............................................................................................................................ 79
FIGURE 35. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 3 (SERIAL/LOCAL-TIM-
ING/FRAME-MASTER) MODE OPERATION ......................................................................................................................... 80
4.2.1.4 MODE 4 - NIBBLE-PARALLEL/LOOP-TIMING MODE OPERATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK ..................................................................................................................................................................... 82
FIGURE 36. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT PAYLOAD DATA INPUT
INTERFACE BLOCK OF THE XRT79L71 FOR MODE 4 (NIBBLE-PARALLEL/LOOP-TIMING) OPERATION .................................. 82
FIGURE 37. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 4 (NIBBLE-PARALLEL/
LOOP-TIMING) MODE OPERATION.................................................................................................................................... 84
4.2.1.5 MODE 5 - NIBBLE-PARALLEL/LOCAL-TIMING/FRAME SLAVE MODE OPERATION FOR THE TRANSMIT PAYLOAD DATA INPUT
INTERFACE BLOCK ................................................................................................................................................... 85
FIGURE 38. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 5 (NIBBLE-PARALLEL/
LOCAL-TIMING/FRAME-SLAVE) MODE OPERATION............................................................................................................ 85
FIGURE 39. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 5 (NIBBLE-PARALLEL/
LOCAL-TIMING/FRAME SLAVE) MODE OPERATION............................................................................................................ 87
4.2.1.6 MODE 6 - NIBBLE-PARALLEL/LOCAL-TIMING/FRAME MASTER MODE OPERATION FOR THE TRANSMIT PAYLOAD DATA IN-
PUT INTERFACE BLOCK ............................................................................................................................................. 87
FIGURE 40. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 6 (NIBBLE-PARALLEL/
LOCAL-TIMING/FRAME MASTER) MODE OPERATION ......................................................................................................... 88
FIGURE 41. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE 6 (NIBBLE-PARALLEL/
LOCAL-TIMING/FRAME MASTER) MODE OPERATION ......................................................................................................... 90
4.2.1.7 OPERATING THE TRANSMIT PAYLOAD DATA INPUT INTERFACE IN THE GAPPED CLOCK MODE ................................ 90
FIGURE 42. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT PAYLOAD DATA INPUT
INTERFACE BLOCK OF THE XRT79L71 FOR GAPPED-CLOCK MODE OPERATIONS ............................................................. 92
4.2.1.8 ACCEPTING AND INSERTING DS3 OVERHEAD BITS VIA THE TRANSMIT PAYLOAD DATA INPUT INTERFACE ............... 92
TABLE 15: HOW THE TRANSMIT DS3 FRAMER BLOCK INTERNALLY GENERATES EACH OF THE OVERHEAD BITS - C-BIT PARITY APPLICATIONS
93
TABLE 16: HOW THE TRANSMIT DS3 FRAMER BLOCK INTERNALLY GENERATES EACH OF THE OVERHEAD BITS - M13/M23 APPLICATIONS
94
4.2.2 TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK................................................................................... 98
FIGURE 43. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS
BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE (WITH THE TRANSMIT OVERHEAD DATA INPUT IN-
TERFACE BLOCK HIGHLIGHTED)........................................................................................................................................ 98
TABLE 17: HOW THE TRANSMIT DS3 FRAMER BLOCK INTERNALLY GENERATES EACH OF THE OVERHEAD BITS - C-BIT PARITY APPLICATIONS
99
TABLE 18: HOW THE TRANSMIT DS3 FRAMER BLOCK INTERNALLY GENERATES EACH OF THE OVERHEAD BITS - M23 APPLICATIONS 100
TABLE 19: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK....... 101
4.2.2.1 OPERATING THE TRANSMIT OVERHEAD DATA INPUT INTERFACE USING METHOD 1 - THE TXOHCLK METHOD ....... 102
FIGURE 44. ILLUSTRATION ON HOW ONE SHOULD INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT OVERHEAD DATA
INPUT INTERFACE BLOCK WHEN USING METHOD 1.......................................................................................................... 103
TABLE 20: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN THE TXOHCLK SIGNAL, SINCE THE TXOHFRAME SIGNAL
WAS LAST SAMPLED "HIGH" TO THE DS3 OVERHEAD BIT THAT IS BEING PROCESSED BY THE TRANSMIT OVERHEAD DATA INPUT
INTERFACE BLOCK ........................................................................................................................................................ 104
FIGURE 45. ILLUSTRATION OF THE SIGNALING THAT MUST OCCUR BETWEEN THE SYSTEM-SIDE TERMINAL EQUIPMENT AND THE TRANSMIT
OVERHEAD DATA INPUT INTERFACE OF THE XRT79L71, IN ORDER TO CONFIGURE THE XRT79L71 TO TRANSMIT THE FERF IN-
DICATOR TO THE REMOTE TERMINAL EQUIPMENT (USING METHOD 1).............................................................................. 106
4.2.2.2 OPERATING THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK USING METHOD 2 - THE TXINCLK/TXOHENABLE
METHOD ................................................................................................................................................................. 107
FIGURE 46. ILLUSTRATION ON HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT OVERHEAD DATA INPUT
INTERFACE BLOCK WHEN USING METHOD 2 ................................................................................................................... 108
TABLE 21: THE RELATIONSHIP BETWEEN THE NUMBER OF PULSES IN THE TXOHENABLE SIGNAL, SINCE THE TXOHFRAME SIGNAL WAS LAST
IV
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