XRT79L71IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71IB' PDF : 441 Pages View PDF
XRT79L71
PRELIMINARY
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
39
2.3.1 THE POWERPC 403 READ-CYCLE........................................................................................................................... 40
FIGURE 10. ILLUSTRATION OF THE BEHAVIOR OF MICROPROCESSOR INTERFACE SIGNALS, DURING A "POWERPC 403" READ OPERATION
41
2.3.2 THE POWERPC 403 WRITE-CYCLE ......................................................................................................................... 41
FIGURE 11. ILLUSTRATION OF THE BEHAVIOR OF MICROPROCESSOR INTERFACE SIGNALS, DURING A "POWERPC 403" WRITE OPERATION
43
2.3.3 INTERFACING THE MICROPROCESSOR INTERFACE TO THE MPC860 MICROPROCESSOR, WHEN CONFIGURED
TO OPERATE IN THE POWERPC 403 MODE ............................................................................................................. 43
FIGURE 12. ILLUSTRATION ON RECOMMENDATION ON HOW TO INTERFACE THE MICROPROCESSOR INTERFACE OF THE XRT79L71 TO THE
MPC860, WHEN CONFIGURED TO OPERATE IN THE POWERPC 403 MODE........................................................................ 44
2.4 THE NEED FOR TXINCLK, IN ORDER TO OPERATE THE MICROPROCESSOR INTERFACE ................ 44
2.5 READING OUT THE DS3/E3 FRAMER BLOCK PERFORMANCE MONITOR REGISTERS ....................... 44
3.0 INTERRUPT STRUCTURE WITHIN THE XRT79L71 ..........................................................................45
TABLE 7: LIST OF ALL OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS WITHIN THE XRT79L71 WHEN CONFIGURED TO
OPERATE IN THE CLEAR-CHANNEL FRAMER MODE ........................................................................................................... 46
TABLE 8: A LISTING OF THE XRT79L71 ATM UNI/PPP/CLEAR-CHANNEL DS3/E3 FRAMER DEVICE INTERRUPT BLOCK REGISTERS -
CLEAR-CHANNEL FRAMER APPLICATIONS ........................................................................................................................ 47
3.1 GENERAL FLOW OF XRT79L71 ATM UNI/PPP/CLEAR-CHANNEL DS3/E3 FRAMER DEVICE INTERRUPT
SERVICING .................................................................................................................................................... 48
TABLE 9: INTERRUPT SERVICE ROUTINE GUIDE FOR THE XRT79L71 .............................................................................................. 50
3.2 INTERRUPT SERVICING FOR THE DS3/E3 FRAMER BLOCK ................................................................... 51
TABLE 10: INTERRUPT SERVICE ROUTINE GUIDE FOR THE DS3/E3 FRAMER BLOCK ........................................................................ 52
4.0 ARCHITECTURAL/FUNCTIONAL DESCRIPTION OF THE XRT79L71 1-CHANNEL DS3/E3 ATM UNI/
PPP/CLEAR-CHANNEL FRAMER WITH LIU IC - CLEAR CHANNEL FRAMER AND HIGH-SPEED HDLC
CONTROLLER MODE APPLICATIONS ...............................................................................................53
FIGURE 13. An Illustration of the Functional Block Diagram of the XRT79L71 when it has been configured to operate in the DS3
Clear-Channel Framer Mode ........................................................................................................................................ 53
4.1 DESCRIPTION OF THE DS3 FRAME STRUCTURE AND OVERHEAD BITS .............................................. 54
FIGURE 14. DS3 FRAME FORMAT FOR C-BIT PARITY ...................................................................................................................... 54
FIGURE 15. DS3 FRAME FORMAT FOR M13/M23 ........................................................................................................................... 55
TABLE 11: THE RELATIONSHIP BETWEEN THE CONTENTS OF BITS 2 (FRAME FORMAT) AND 6 (ISDS3) WITHIN THE FRAMER OPERATING MODE
REGISTER, AND THE RESULTING FRAMING FORMAT .......................................................................................................... 56
TABLE 12: C-BIT FUNCTIONS FOR THE DS3, C-BIT PARITY FRAMING FORMAT.................................................................................. 57
FIGURE 16. A SIMPLE ILLUSTRATION OF THE LOCATIONS OF THE SOURCE, MID-NETWORK AND SINK TERMINAL EQUIPMENT (FOR CP-BIT
PROCESSING)................................................................................................................................................................. 59
FIGURE 17. A SIMPLE ILLUSTRATION OF AN EXAMPLE OF A MID-NETWORK TERMINAL EQUIPMENT ................................................... 60
FIGURE 18. AN ILLUSTRATION OF A CONDITION IN WHICH AIS WOULD NEED TO BE TRANSMITTED ..................................................... 62
THE DS3 IDLE CONDITION SIGNAL................................................................................................................63
FIGURE 19. THE BIT-FORMAT OF THE FEAC MESSAGE .................................................................................................................. 63
FIGURE 20. A SIMPLE ILLUSTRATION OF A NEAR-END TERMINAL EXCHANGING DS3 DATA WITH A REMOTE TERMINAL, IN AN UN-ERRED MAN-
NER................................................................................................................................................................................ 64
FIGURE 21. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL TRANSMITTING THE UN-ERRED INDICATION TO THE REMOTE TERMINAL
EQUIPMENT..................................................................................................................................................................... 64
FIGURE 22. A SIMPLE ILLUSTRATION OF A NEAR-END TERMINAL DETECTING FRAMING BIT ERRORS WITHIN ITS INCOMING DS3 SIGNAL65
FIGURE 23. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL EQUIPMENT TRANSMITTING THE FEBE/REI INDICATOR TO THE REMOTE
TERMINAL EQUIPMENT ..................................................................................................................................................... 65
FIGURE 24. A SIMPLE ILLUSTRATION OF A NEAR-END TERMINAL EXCHANGING DS3 DATA WITH A REMOTE TERMINAL, IN AN UN-ERRED MAN-
NER................................................................................................................................................................................ 66
FIGURE 25. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL TRANSMITTING THE UN-ERRED INDICATION THE REMOTE TERMINAL
EQUIPMENT..................................................................................................................................................................... 66
FIGURE 26. A SIMPLE ILLUSTRATION OF A NEAR-END TERMINAL DECLARING THE LOS DEFECT CONDITION WITH ITS INCOMING DS3 SIGNAL
67
FIGURE 27. A SIMPLE ILLUSTRATION OF THE NEAR-END TERMINAL EQUIPMENT TRANSMITTING THE FERF/RDI INDICATOR TO THE REMOTE
TERMINAL EQUIPMENT ..................................................................................................................................................... 67
4.2 THE TRANSMIT DIRECTION - DS3 CLEAR-CHANNEL FRAMER APPLICATIONS ................................... 68
FIGURE 28. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY WHEN THE XRT79L71 HAS BEEN
CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE.......................................................................... 68
4.2.1 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK...................................................................................... 69
FIGURE 29. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY, WHEN THE XRT79L71 HAS BEEN
CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE (WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE
BLOCK HIGHLIGHTED....................................................................................................................................................... 69
TABLE 13: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ........... 70
OPERATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK .......................................................72
III
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