ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
It is best practice to use the ADE7868A/ADE7878A in PSM2
mode when the PGA1 gain is 1 or 2. PGA1 represents the gain
in the current channel datapath. Do not use the ADE7868A or
ADE7878A in PSM2 mode when the PGA1 gain is 4, 8, or 16.
Two PSM2 modes of operation are available: PSM2 interrupt
mode and PSM2 IRQ1 only mode. The PSM2 interrupt mode is
the default mode. If the use of an external timer is possible, use
the PSM2 IRQ1 only mode.
The PSM2 level threshold comparison is based on a peak
detection methodology. The peak detection circuit makes the
comparison based on the positive terminal current channel
input, IAP, IBP, and ICP (see Figure 24). If differential inputs are
applied to the current channels, Figure 24 shows the differential
antiphase signals at each current input terminal, IxP and IxN, and
the net differential current, IxP − IxN.
+V p-p/2
+V p-p
• IRQ1 pulled low: missing neutral tamper condition detected.
When the IRQ1 pin is pulled low at the end of the measure-
ment period, it indicates that at least one current input is
above the defined threshold and current is flowing through
the system, although no voltage is present at the ADE7868A/
ADE7878A pins. This condition indicates the occurrence
of a missing neutral tamper condition. At this point, the
external microprocessor sets the ADE7868A/ADE7878A to
PSM1 mode, measures the mean absolute values of the phase
currents, and integrates the energy based on these values and
the nominal voltage.
Setting the Measurement Period
The measurement period is defined by Bits[7:3] (LPLINE[4:0])
of the LPOILVL register (Address 0xEC00). The measurement
period is independent of the line frequency and is defined as
Measurement Period (sec) = 0.02 × (LPLINE[4:0] + 10)
IxP
Setting the Threshold
–V p-p/2
+V p-p/2
IxP – IxN
The threshold is defined by Bits[2:0] (LPOIL[2:0]) of the LPOILVL
register (see Table 10). The threshold level is for signal levels with
IxN
–V p-p/2
–V p-p
the PGA set to 1. When LPOIL[2:0] = 111, the absolute value of
the threshold typically varies by up to ±30%.
Table 10. LPOILVL Register
(a)
Bits Bit Name Value Description
[2:0] LPOIL[2:0]
Input signal levels that correspond
to the following thresholds:
IxP
VREF
PEAK DETECT CIRCUIT
TAMPER
INDICATION
000 71 mV rms
001 Reserved
010 Reserved
011 1 mV rms
100 Reserved
101 Reserved
(b)
110 Reserved
Figure 24. PSM2 Low Power Mode Peak Detection
111 0.471 mV rms
PSM2 Interrupt Mode (Default)
In PSM2 interrupt mode, the ADE7868A/ADE7878A compare
all phase currents against the programmable threshold for the
programmable period of time. During this time, if one phase
current exceeds the threshold, a counter is incremented. If a
[7:3] LPLINE[4:0]
Default value is 00000.
Measurement period in PSM2
interrupt mode is
0.02 × (LPLINE[4:0] + 10) sec
Measurement period in
PSM2 IRQ1 only mode is
single phase counter is greater than or equal to LPLINE[4:0] + 1
at the end of the measurement period, the IRQ1 pin is pulled
0.02 × (LPLINE[4:0] + 1) sec
low. If every phase counter remains below LPLINE[4:0] + 1 at
the end of the measurement period, the IRQ0 pin is pulled low.
In this way, a combination of the IRQ0 and IRQ1 pins is used to
determine the outcome of the measurement as follows:
Figure 25 shows the typical variation around each threshold
level; the gray regions in Figure 25 indicate where the feature
may not yield expected and uniform results. The current levels
outside this gray range help detect a tamper condition. For
• IRQ0 pulled low: no tamper detected. When the IRQ0 pin
is pulled low at the end of a measurement period, it indicates
that all phase currents are below the defined threshold and,
example, setting the threshold to 0.471 mV rms provides
dependable tamper detection results for current levels above
0.707 mV rms and below 0.353 mV rms.
therefore, no current is flowing through the system. In this
case, the device does not detect a tamper condition. The
external microprocessor sets the ADE7868A/ADE7878A to
PSM3 sleep mode.
Rev. C | Page 22 of 96
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