ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
POWER-UP PROCEDURE
3.3V – 10%
2.5V ± 10%
ADE7854A/ADE7858A/ADE7868A/ADE7878A
ADE78xxA
PSM0 READY
0V
MICROPROCESSOR
SETS PM1 PIN TO 0;
APPLY VDD TO IC
~26ms
~40ms
POR TIMER
TURNED ON
ADE78xxA
FULLY
POWERED UP
Figure 27. Power-Up Procedure
MICROPROCESSOR
MAKES THE
RSTDONE CHOICE BETWEEN
INTERRUPT I2C AND SPI
TRIGGERED
The ADE7854A/ADE7858A/ADE7868A/ADE7878A contain
an on-chip power supply monitor that supervises the power
supply (VDD). At power-up, the device is inactive until VDD
reaches 2.5 V ± 10%. When VDD crosses this threshold, the
power supply monitor keeps the device in the inactive state for
an additional 26 ms to allow VDD to rise to 3.3 V − 10%, the
minimum recommended supply voltage.
The PM0 and PM1 pins have internal pull-up resistors, but it is
necessary to set the PM1 pin to Logic 0 either through a
microcontroller or by grounding the PM1 pin externally, before
powering up the chip. The PM0 pin can remain open as it is
held high, due to the internal pull-up resistor. This ensures that
ADE7854A/ADE7858A/ADE7868A/ADE7878A always power
up in PSM0 (normal) mode. The time taken from the chip
being powered up completely to the state where all functionality
is enabled, is about 40 ms (see Figure 27). It is necessary to
ensure that the RESET pin is held high during the entire power-
up procedure.
If PSM0 mode is the only desired power mode, the PM1 pin can
be tied to ground externally. When the ADE7854A/ADE7858A/
ADE7868A/ADE7878A enter PSM0 mode, the I2C port is the
active serial port. To use the SPI port, toggle the SS/HSA pin three
times from high to low.
To lock I2C as the active serial port, set Bit 1 (I2C_LOCK) of the
CONFIG2 register to 1. From this moment, the device ignores
spurious toggling of the SS/HSA pin, and a switch to the SPI
port is no longer possible.
If SPI is the active serial port, any write to the CONFIG2 register
locks the port, and a switch to the I2C port is no longer possible.
To use the I2C port, the ADE7854A/ADE7858A/ADE7868A/
ADE7878A must be powered down or the device must be reset
by setting the RESET pin low. After the serial port is locked, the
serial port selection is maintained when the device changes
from one PSMx power mode to another.
Immediately after entering PSM0 mode, all registers in the
ADE7854A/ADE7858A/ADE7868A/ADE7878A are set to their
default values, including the CONFIG2 and LPOILVL registers.
The ADE7854A/ADE7858A/ADE7868A/ADE7878A signal the
end of the transition period by pulling the IRQ1 interrupt pin low
and setting Bit 15 (RSTDONE) in the STATUS1 register to 1.
This bit is cleared to 0 during the transition period and is set to
1 when the transition ends. Writing the STATUS1 register with
the RSTDONE bit set to 1 clears the status bit and returns the
IRQ1 pin high. Because RSTDONE is an unmaskable interrupt,
Bit 15 (RSTDONE) in the STATUS1 register must be cancelled
for the IRQ1 pin to return high. Wait until the IRQ1 pin goes low
before accessing the STATUS1 register to test the state of the
RSTDONE bit. At this point, as a good programming practice,
cancel all other status flags in the STATUS1 and STATUS0 registers
by writing the corresponding bits with 1.
Initially, the DSP is in idle mode and, therefore, does not
execute any instructions. This is the moment to initialize all
registers in the ADE7854A, ADE7858A, ADE7868A, or
ADE7878A. See the Digital Signal Processor section for the
proper procedure to initialize all registers and start the
metering.
If the supply voltage, VDD, falls lower than 2.5 V ± 10%,
the ADE7854A/ADE7858A/ADE7868A/ADE7878A enter
an inactive state, which means that no measurements or
computations are executed.
HARDWARE RESET
The ADE7854A, ADE7858A, ADE7868A, and ADE7878A have
a RESET pin. When the ADE7854A, ADE7858A, ADE7868A,
or ADE7878A is in PSM0 mode and the RESET pin is set low,
the device enters the hardware reset state. The device must be in
PSM0 mode to execute a hardware reset. Setting the RESET pin
low while the device is in PSM1, PSM2, or PSM3 mode has no
effect on the device.
Rev. C | Page 25 of 96
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