ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
Current Channel High-Pass Filter
The ADC outputs can contain a dc offset. This offset may create
errors in power and rms calculations. High-pass filters (HPFs)
are placed in the signal path of the phase and neutral currents
and of the phase voltages. When enabled, the HPF eliminates
any dc offset on the current channel. All filters are implemented
in the DSP and, by default, they are all enabled: the 24-bit HPFDIS
register is cleared to 0x000000. Disable all filters by setting
HPFDIS to any nonzero value.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7854A, ADE7858A, ADE7868A, and
ADE7878A work on 32-, 16-, or 8-bit words. The HPFDIS
register is accessed as a 32-bit register with eight MSBs padded
with 0s (see Figure 37).
31
24 23
0
0000 0000
24-BIT NUMBER
Figure 37. 24-Bit HPFDIS Register Transmitted as a 32-Bit Word
Current Channel Sampling
The waveform samples of the current channel are taken at the
output of the HPF at a rate of 8 kSPS and stored in the 24-bit
signed registers, IAWV, IBWV, ICWV, and INWV (ADE7868A
and ADE7878A only). All power and rms calculations remain
uninterrupted during this process. Bit 17 (DREADY) in the
STATUS0 register is set when the IAWV, IBWV, ICWV, and
INWV registers are available to be read using the I2C or SPI
serial port. Setting Bit 17 (DREADY) in the MASK0 register
enables an interrupt to be set when the DREADY flag is set. See
the Digital Signal Processor section for more information about
the DREADY bit.
As stated in the Current Waveform Gain Registers section,
the serial ports of the ADE7854A/ADE7858A/ADE7868A/
ADE7878A work on 32-, 16-, or 8-bit words. When the IAWV,
IBWV, ICWV, and INWV 24-bit signed registers are read from
the device (INWV is available on ADE7868A/ADE7878A only),
they are transmitted sign extended to 32 bits (see Figure 38).
31
24 23 22
0
24-BIT SIGNED NUMBER
BITS[31:24] ARE
EQUAL TO BIT 23
BIT 23 IS A SIGN BIT
Figure 38. 24-Bit IxWV Registers Transmitted as 32-Bit Signed Words
The ADE7854A/ADE7858A/ADE7868A/ADE7878A contain a
high speed data capture (HSDC) port that is specially designed
to provide fast access to the waveform sample registers. For more
information, see the HSDC Interface section.
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
The di/dt sensor detects changes in the magnetic field caused by
the ac current. Figure 39 shows the principle of a di/dt current
sensor.
MAGNETIC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
Figure 39. Principle of a di/dt Current Sensor
The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. The
changes in the magnetic flux density passing through a conductor
loop generate an electromotive force (EMF) between the two
ends of the loop. The EMF is a voltage signal that is propor-
tional to the di/dt of the current. The mutual inductance
between the current carrying conductor and the di/dt sensor
determine the voltage output from the di/dt current sensor.
The di/dt sensor requires filtering of the current signal before
using it for power measurement. On each phase and neutral
current datapath, there is a built-in digital integrator to recover
the current signal from the di/dt sensor. The digital integrator
is disabled by default when the ADE7854A/ADE7858A/
ADE7868A/ADE7878A are powered up and after a reset.
Setting Bit 0 (INTEN) of the CONFIG register turns on the
integrator. Figure 40 and Figure 41 show the magnitude and
phase response of the digital integrator.
Note that the integrator has a −20 dB/dec attenuation and an
approximately −90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. However, the di/dt
sensor has a 20 dB/dec gain associated with it, and it generates
significant high frequency noise. An antialiasing filter of at least
the second order is required to avoid noise aliasing back in the
band of interest when the ADC is sampling (see the Antialiasing
Filter section).
50
0
–50
0.01
0.1
0
1
10
100
FREQUENCY (Hz)
1000
–50
–100
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
Figure 40. Combined Gain and Phase Response of the Digital Integrator
Rev. C | Page 30 of 96
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