ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
THEORY OF OPERATION
ANALOG INPUTS
The ADE7868A/ADE7878A have seven analog inputs forming
current and voltage channels. The ADE7854A/ADE7858A have
six analog inputs but the neutral current is removed from these
devices.
The current channels consist of four pairs of fully differential
voltage inputs: IAP and IAN, IBP and IBN, ICP and ICN, and
INP and INN. These voltage input pairs have a maximum
differential signal of ±0.5 V peak. In addition, the maximum
signal level on analog inputs for each IxP/IxN pair is ±0.5 V
peak with respect to AGND. The maximum common-mode
signal allowed on the inputs is ±25 mV. Figure 28 shows a
schematic of the input for the current channels and their
relationship to the maximum common-mode voltage.
V1 + V2
DIFFERENTIAL INPUT
V1 + V2 = 500mV MAX PEAK
COMMON MODE
VCM = ±25mV MAX
+500mV
VCM
–500mV
IAP, IBP,
V1
ICP, OR INP
VCM
V2
IAN, IBN,
ICN, OR INN
Figure 28. Maximum Input Level, Current Channels, Gain = +1
All inputs have a programmable gain amplifier (PGA) with a
possible gain selection of 1, 2, 4, 8, or 16. The gain of the IAx,
IBx, and ICx inputs is set in Bits[2:0] (PGA1[2:0]) of the gain
register. For the ADE7868A and ADE7878A only, the gain of
the INx channel input is set in Bits[5:3] (PGA2[2:0]) of the gain
register; thus, a different gain from the IAx, IBx, or ICx inputs is
possible. See Table 41 for information about the gain register. The
voltage channel has three single-ended voltage inputs: VAP,
VBP, and VCP. These single-ended voltage inputs have a maximum
input voltage of ±0.5 V with respect to VN. In addition, the
maximum signal level on analog inputs for VxP and VN is
±0.5 V with respect to AGND. The maximum common-mode
signal allowed on the inputs is ±25 mV. See Figure 29 for a
schematic of the voltage channel inputs and their relationship to
the maximum common-mode voltage.
SINGLE-ENDED INPUT
V1 = 500mV MAX PEAK
V1
COMMON MODE
VCM = ±25mV MAX
+500mV
VCM
–500mV
VAP, VBP,
V1 OR VCP
VN
VCM
Figure 29. Maximum Input Level, Voltage Channels, Gain = +1
All inputs have a programmable gain with a possible gain
selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6]
(PGA3[2:0]) in the gain register (see Table 41).
Figure 30 shows how the gain selection from the gain register
works in both the current and voltage channels.
GAIN
SELECTION
IxP, VyP
VIN
IxN, VN
K × VIN
NOTES
1. x = A, B, C, N.
y = A, B, C.
Figure 30. PGA in Current and Voltage Channels
ANALOG-TO-DIGITAL CONVERSION
The ADE7868A/ADE7878A have seven Σ-Δ analog-to-digital
converters (ADCs), and the ADE7854A/ ADE7858A have six
Σ-Δ ADCs.
In PSM0 mode, all ADCs are active.
In PSM1 mode, only the ADCs that measure the Phase A,
Phase B, and Phase C currents are active. The ADCs that
measure the neutral current and the A, B, and C phase
voltages are turned off.
In PSM2 and PSM3 modes, the ADCs are powered down
to minimize power consumption.
For simplicity, the block diagram in Figure 31 shows a first-
order Σ-Δ ADC. The converter is composed of the Σ-Δ modulator
and the digital low-pass filter.
ANALOG
LOW-PASS FILTER
R
C
CLKIN/16
INTEGRATOR
LATCHED
+
–
+ COMPARATOR
–
VREF
DIGITAL
LOW-PASS
FILTER
24
.....10100101.....
1-BIT DAC
Figure 31. First-Order -∆ ADC
The Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7854A/ADE7858A/ADE7868A/ADE7878A,
the sampling clock is equal to 1.024 MHz (CLKIN/16).
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal.
When the loop gain is high enough, the average value of the
DAC output (and, therefore, the bit stream) can approach that
of the input signal level. For any given input value in a single
sampling interval, the data from the 1-bit ADC is virtually
meaningless. Only when a large number of samples are
averaged is a meaningful result obtained. This averaging occurs
in the second part of the ADC (the digital low-pass filter). By
averaging a large number of bits from the modulator, the low-
pass filter can produce 24-bit data-words that are proportional
to the input signal level.
Rev. C | Page 27 of 96
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