ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
The Σ-Δ ADC uses two techniques to achieve high resolution
from what is essentially a 1-bit conversion technique. The first
technique is oversampling. Oversampling means that the signal
is sampled at a rate (frequency) that is many times higher than
the bandwidth of interest. For example, the sampling rate in the
ADE7854A/ADE7858A/ADE7868A/ADE7878A is 1.024 MHz,
and the bandwidth of interest is 40 Hz to 2 kHz.
Oversampling has the effect of spreading the quantization noise
(noise due to sampling) over a wider bandwidth. With the noise
spread more thinly over a wider bandwidth, the quantization noise
in the band of interest lowers, as shown in Figure 32. However,
oversampling alone is not efficient enough to improve the signal-
to-noise ratio (SNR) in the band of interest. For example, an
oversampling factor of 4 is required just to increase the SNR by a
mere 6 dB (one bit). To keep the oversampling ratio at a reasonable
level, it is possible to shape the quantization noise so that the
majority of the noise lies at the higher frequencies.
the band of interest for metering, that is, 40 Hz to 2 kHz. To
attenuate the high frequency noise (near 1.024 MHz) and
prevent the distortion of the band of interest, a low-pass filter
(LPF) must be introduced.
For conventional current sensors, use one RC filter with a corner
frequency of 5 kHz to achieve sufficiently high attenuation at
the sampling frequency of 1.024 MHz. The 20 dB per decade
attenuation of this filter is usually sufficient to eliminate the
effects of aliasing for conventional current sensors. However, for a
di/dt sensor, such as a Rogowski coil, the sensor has a 20 dB per
decade gain. This neutralizes the 20 dB per decade attenuation
produced by the LPF. Therefore, when using a di/dt sensor, take
care to offset the 20 dB per decade gain. One simple approach is
to cascade one additional RC filter, thereby producing a −40 dB
per decade attenuation.
ALIASING EFFECTS
SAMPLING
FREQUENCY
In the Σ-Δ modulator, the noise is shaped by the integrator,
which has a high-pass-type response for the quantization noise.
This is the second technique used to achieve high resolution. The
result is that most of the noise is at the higher frequencies where
the digital low-pass filter removes it. This noise shaping is shown in
Figure 32.
SIGNAL
ANTIALIAS FILTER
DIGITAL FILTER (RC)
SHAPED NOISE
SAMPLING
FREQUENCY
NOISE
0 24
512
FREQUENCY (kHz)
SIGNAL
HIGH RESOLUTION
OUTPUT FROM
DIGITAL LPF
1024
NOISE
0
24
512
FREQUENCY (kHz)
IMAGE
FREQUENCIES
1024
Figure 33. Aliasing Effects
ADC Transfer Function
All ADCs in the ADE7854A/ADE7858A/ADE7868A/
ADE7878A are designed to produce the same 24-bit signed
output code for the same input signal level. With a full-scale
input signal of 0.5 V and an internal reference of 1.2 V, the ADC
output code is nominally 5,928,256 (0x5A7540). The code from
the ADC can vary between 0x800000 (−8,388,608) and 0x7FFFFF
(+8,388,607); this is equivalent to an input signal level of ±0.707 V.
However, for specified performance, do not exceed the nominal
range of ±0.5 V peak; ADC performance is guaranteed only for
input signals lower than ±0.5 V peak.
0 24
512
FREQUENCY (kHz)
1024
Figure 32. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
Antialiasing Filter
Figure 31 shows an analog low-pass filter (RC) on the input to
the ADC. This filter is placed outside the ADE7854A/ADE7858A/
ADE7868A/ADE7878A; its role is to prevent aliasing. Aliasing
is an artifact of all sampled systems, as shown in Figure 33. Aliasing
means that frequency components in the input signal to the ADC,
which are higher than half the sampling rate of the ADC, appear in
the sampled signal at a frequency below half the sampling rate.
Frequency components above half the sampling frequency (also
known as the Nyquist frequency, that is, 512 kHz) are imaged or
folded back down below 512 kHz. This happens with all ADCs
regardless of the architecture. In the example shown, only frequen-
cies near the sampling frequency, that is, 1.024 MHz, move into
CURRENT CHANNEL ADC
Figure 35 shows the ADC and signal processing path for the
IA current channel. It is the same for the IB and IC current
channels. The ADC outputs are signed, twos complement,
24-bit data-words and are available at a rate of 8 kSPS (thousand
samples per second). With the specified full-scale analog input
signal of ±0.5 V peak, the ADC produces its maximum output
code value; the ADC output swings between −5,928,256
(0xA58AC0) and +5,928,256 (0x5A7540). Figure 35 shows a
full-scale voltage signal applied to the differential inputs (IAP
and IAN). The IN current channel corresponds to the neutral
current of a 3-phase system (available in the ADE7868A and
ADE7878A only). If no neutral line is present, connect this
input to AGND. The datapath of the neutral current is similar
to the path of the phase currents (see Figure 36).
Rev. C | Page 28 of 96
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