ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
RATIO TO
FULL SCALE
79mV rms
71mV rms
64mV rms
LPOIL[2:0] = 000
1.18mV rms
1mV rms
DETECTS
NONTAMPER
CONDITIONS
BELOW
THIS LEVEL
0.88mV rms
0.707mV rms
0.471mV rms
LPOIL[2:0] = 011
LPOIL[2:0] = 111
DETECTS
TAMPER
CONDITIONS
ABOVE
THIS LEVEL
0.353mV rms
Figure 25. Variation Around Each Threshold Setting
Figure 26 shows the behavior of the ADE7868A/ADE7878A
PSM2 mode when LPLINE[4:0] = 2. The test period is 12 cycles
at 50 Hz (240 ms); the Phase A current rises above the LPOIL[2:0]
threshold five times. Because the counter value is above the
internal counter requirement of LPLINE[4:0] + 1, the IRQ1 pin
is pulled low at the end of the test period. This result suggests
that a missing neutral tamper condition has occurred.
PSM2 IRQ1 Only Mode
The PSM2 IRQ1 only mode uses only the IRQ1 pin to indicate
a tamper event. If no tamper event has occurred, no signal is
provided by the ADE7868A or ADE7878A.
To disable the IRQ0 pin and thus enable the PSM2 IRQ1
only mode, set Bit 2 (IRQ0_DIS) in the CONFIG2 register
(Address 0xEC01) to 1. Selecting this mode defines the
recommended measurement period using the following
formula:
Recommended Measurement Period (sec) =
0.02 × (LPLINE[4:0] + 1)
Because a wait is required during this measurement period, use
an external timer before checking the status of the IRQ1 interrupt.
The measurement period can be longer than the recommended
period because the internal phase counter continues to increment
for the entire time that the device is in PSM2 mode. Switching
to PSM3 mode and then back to PSM2 mode causes the device
to enter the PSM2 interrupt mode (the default PSM2 mode).
PSM3 SLEEP MODE (ALL DEVICES)
PSM3 sleep mode is available on all devices: ADE7854A,
ADE7858A, ADE7868A, and ADE7878A. In sleep mode, most
of the internal circuits in the devices are turned off and the current
consumption is at its lowest level. When configuring the device
for sleep mode, set the RESET, SCLK/SCL, MOSI/SDA, and
SS/HSA pins high.
In PSM3 sleep mode, the I2C, HSDC, and SPI ports are not
functional.
LPOIL[2:0]
THRESHOLD
IA CURRENT
LPLINE[4:0] = 2
MEASUREMENT PERIOD = 12 CYCLES (50Hz)
IRQ1
AS PHASE COUNTER > LPLINE[4:0] +1, IRQ1 IS TRIGGERED
Figure 26. PSM2 Interrupt Mode Triggering IRQ1 Pin for LPLINE[4:0] = 2 (50 Hz Systems)
Rev. C | Page 23 of 96
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