ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
When the ADE7854A, ADE7858A, ADE7868A, or ADE7878A
is in PSM0 mode and the RESET pin is toggled from high to low
and then back to high after at least 10 µs, all registers are reset
to their default values, including the CONFIG2 and LPOILVL
registers.
The device signals the end of the transition period by pulling
the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in
the STATUS1 register to 1. This bit is cleared to 0 during the
transition period and is reset to 1 when the transition ends.
Writing to the STATUS1 register with the RSTDONE bit set to
1 clears the status bit and returns the IRQ1 pin high.
After a hardware reset, the DSP is in idle mode and, therefore,
does not execute any instructions.
Because the I2C port is the default serial port of the ADE7854A/
ADE7858A/ADE7868A/ADE7878A, it becomes active after a
reset. If the SPI is the port used by the external microprocessor,
the procedure to enable it must be repeated immediately after
the RESET pin is toggled back to high (for more information,
see the Serial Interface Selection section).
After a hardware reset, initialize all registers of the ADE7854A/
ADE7858A/ADE7868A/ADE7878A registers, enable data memory
RAM protection, and then write 0x0001 to the run register to
start the DSP. For more information about data memory RAM
protection and the run register, see the Digital Signal Processor
section.
SOFTWARE RESET
Bit 7 (SWRST) in the CONFIG register manages the software
reset functionality in PSM0 mode. The default value of this bit
is 0. Setting Bit 7 to 1 causes the ADE7854A/ADE7858A/
ADE7868A/ADE7878A to enter the software reset state. In this
state, all internal registers except for CONFIG2 and LPOILVL
are reset to their default values. The selected serial port, I2C or
SPI, remains unchanged if the lock-in procedure was executed
(see the Serial Interface Selection section).
When the software reset ends, Bit 7 (SWRST) in the CONFIG
register is cleared to 0, the IRQ1 interrupt pin is set low, and
Bit 15 (RSTDONE) in the STATUS1 register is set to 1. The
RSTDONE bit is cleared to 0 during the transition period and
is reset to 1 when the transition ends. Writing to the STATUS1
register with the RSTDONE bit set to 1 clears the status bit and
resets the IRQ1 pin high.
After software reset, the DSP is in idle mode and, therefore,
does not execute any instructions. Take the following steps to
restart the DSP:
1. Initialize all ADE7854A/ADE7858A/ADE7868A/
ADE7878A registers.
2. Enable the data memory RAM protection.
3. Write 0x0001 to the run register to start the DSP. For more
information about data memory RAM protection and the
run register, see the Digital Signal Processor section.
The software reset functionality is not available in PSM1, PSM2,
or PSM3 mode.
Rev. C | Page 26 of 96
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