ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
Voltage Channel HPF
As explained in the Current Channel High-Pass section, the
ADC outputs can contain a dc offset that can create errors in
power and rms calculations. HPFs are placed in the signal path
of the phase voltages, similar to the ones in the current
channels. The HPFDIS register enables or disables the filters.
See the Current Channel High-Pass section for more
information.
Voltage Channel Sampling
The waveform samples of the voltage channel are taken at the
output of the HPF at a rate of 8 kSPS and stored into VAWV,
VBWV, and VCWV 24-bit signed registers. All power and rms
calculations remain uninterrupted during this process. Bit 17
(DREADY) in the STATUS0 register is set when the VAWV,
VBWV, and VCWV registers are available to be read using the
I2C or SPI serial port. Setting Bit 17 (DREADY) in the MASK0
register enables an interrupt to be set when the DREADY flag is
set. For more information about the DREADY bit, see the
Digital Signal Processor section.
As stated in the Current Waveform Gain Registers section,
the serial ports of the ADE7854A/ADE7858A/ADE7868A/
ADE7878A work on 32-, 16-, or 8-bit words. Similar to the
registers shown in Figure 38, the VAWV, VBWV, and VCWV
24-bit signed registers are transmitted sign extended to 32 bits.
The ADE7854A/ADE7858A/ADE7868A/ADE7878A each
contain an HSDC port especially designed to provide fast access
to the waveform sample registers. See the HSDC Interface section
for more information.
CHANGING THE PHASE VOLTAGE DATAPATH
The ADE7854A/ADE7858A/ADE7868A/ADE7878A can direct
one phase voltage input to the computational datapath of another
phase. For example, Phase A voltage can be introduced in the
Phase B computational datapath, which means all powers
computed by the ADE7854A/ADE7858A/ADE7868A/ADE7878A
in Phase B are based on Phase A voltage and Phase B current.
Bits[9:8] (VTOIA[1:0]) of the CONFIG register manage what
phase voltage is directed to Phase A computational data path. If
VTOIA[1:0] = 00 (default value), the Phase A voltage is directed
to the Phase A computational data path. If VTOIA[1:0] = 01,
the Phase B voltage is directed to the Phase A computational
data path. If VTOIA[1:0] = 10, the Phase C voltage is directed
to the Phase A computational data path. If VTOIA[1:0] = 11,
the ADE7854A/ADE7858A/ADE7868A/ADE7878A behave as
if VTOIA[1:0] = 00.
Bits[11:10] (VTOIB[1:0]) of the CONFIG register manage
what phase voltage is directed to the Phase B computational
data path. If VTOIB[1:0] = 00 (default value), the Phase B
voltage is directed to the Phase B computational data path.
If VTOIB[1:0] = 01, the Phase C voltage is directed to the
Phase B computational data path. If VTOIB[1:0] = 10, the Phase A
voltage is directed to the Phase B computational data path. If
VTOIB[1:0] = 11, the ADE7854A/ADE7858A/ADE7868A/
ADE7878A behave as if VTOIB[1:0] = 00.
Bits[13:12] (VTOIC[1:0]) of the CONFIG register manage what
phase voltage is directed to the Phase C computational data
path. If VTOIC[1:0] = 00 (default value), the Phase C voltage is
directed to Phase C computational data path, if VTOIC[1:0] =
01, the Phase A voltage is directed to the Phase C computational
data path. If VTOIC[1:0] = 10, the Phase B voltage is directed to
the Phase C computational data path. If VTOIC[1:0] = 11, the
ADE7854A/ADE7858A/ADE7868A/ADE7878A behave as if
VTOIC[1:0] = 00.
IA
APHCAL
VA
IB
PHASE A
COMPUTATIONAL
DATAPATH
VTOIB[1:0] = 10,
PHASE A VOLTAGE
DIRECTED
TO PHASE B
BPHCAL
VB
IC
PHASE B
COMPUTATIONAL
DATAPATH
VTOIC[1:0] = 10,
PHASE B VOLTAGE
DIRECTED
TO PHASE C
CPHCAL
VC
PHASE C
COMPUTATIONAL
DATAPATH
VTOIA[1:0] = 10,
PHASE C VOLTAGE
DIRECTED
TO PHASE A
Figure 43. Phase Voltages Used in Different Datapaths
Figure 43 presents the case in which Phase A voltage is used in
the Phase B datapath, phase B voltage is used in the Phase C
datapath, and phase C voltage is used in the phase A datapath.
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
The ADE7854A/ADE7858A/ADE7868A/ADE7878A have a
zero-crossing (ZX) detection circuit on the phase current and
voltage channels. The neutral current datapath does not contain
a zero-crossing detection circuit. Zero-crossing events serve as a
time base for various power quality measurements and in the
calibration process.
The output of LPF1 generates zero-crossing events. The low-pass
filter eliminates all harmonics of 50 Hz and 60 Hz systems, and
helps identify the zero-crossing events on the fundamental com-
ponents of both current and voltage channels.
The digital filter has a pole at 80 Hz and is clocked at 256 kHz.
As a result, there is a phase lag between the analog input signal
(one of each pair of IA, IB, IC, VA, VB, and VC signals) and the
output of LPF1. The error in ZX detection is 0.0703° for 50 Hz
systems (0.0843° for 60 Hz systems). The phase lag response of
LPF1 results in a time delay of approximately 31.4° or 1.74 ms
(at 50 Hz) between its input and output. The overall delay
between the zero crossing on the analog inputs and ZX detection
obtained after LPF1 is about 39.6° or 2.2 ms (at 50 Hz). The
ADC and HPF introduce the additional delay. To assure good
Rev. C | Page 32 of 96
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