ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
To find the phase that triggered the interrupt
1. Read the STATUS1 register and then immediately read the
PHSTATUS register.
2. Clear Status Bit 17 (OI) in the STATUS1 register and clear
Bits[5:3] (OIPHASE[2:0]) in the PHSTATUS register.
3. Set the IRQ1 pin to high by writing to the STATUS1
register with the status bit set to 1.
Note that overvoltage detection uses a similar process.
Overvoltage and Overcurrent Level Set
The content of the overvoltage (OVLVL) and overcurrent
(OILVL) 24-bit unsigned registers is compared to the absolute
value of the voltage and current channels. The maximum value of
these registers is the maximum value of the HPF outputs, that
is, 5,928,256 (0x5A7540); an overvoltage or overcurrent
condition is never detected when either the OVLVL or OILVL
register is equal to this value. Writing 0x0 to these registers
signifies continuous detection for overvoltage and overcurrent
conditions, permanently triggering the corresponding interrupts.
As stated in the Current Waveform Gain Registers section, the
serial ports of the device work on 32-, 16-, or 8-bit words.
Similar to the register presented in Figure 37, the OILVL and
OVLVL registers are accessed as 32-bit registers with the eight
MSBs padded with 0s.
Neutral Current Mismatch—ADE7868A and ADE7878A
Neutral current mismatch is available in the ADE7868A and
ADE7878A only. In 3-phase systems, the neutral current is
equal to the algebraic sum of the phase currents
IN(t) = IA(t) + IB(t) + IC(t)
(8)
A mismatch between these two quantities indicates that a
tamper situation may have occurred in the system.
The ADE7868A/ADE7878A compute the sum of the phase
currents by adding the content of the IAWV, IBWV, and ICWV
registers and storing the result into the ISUM 28-bit signed
register, as follows:
ISUM(t) = IA(t) + IB(t) + IC(t)
(9)
ISUM is computed every 125 μs (8 kHz frequency), the rate at
which the current samples are available; Bit 17 (DREADY) in
the STATUS0 register signals when the ISUM register can be
read. For more information about the DREADY bit, see the
Digital Signal Processor section.
To recover the ISUM(t) value from the ISUM register, use the
following expression:
ISUM(t)
ISUM[27:0]
ADCMAX
I FS
(10)
where:
ADCMAX = 5,928,256, the ADC output when the input is at
full scale.
IFS is the full-scale ADC phase current.
Note that the ADE7868A/ADE7878A also compute the rms
of ISUM and store it in the NIRMS register when Bit 0 in the
CONFIG_A register (INSEL) is set to 1 (see the Current RMS
Calculation section for more information).
The ADE7868A/ADE7878A compute the difference between
the absolute values of ISUM and the neutral current from the
INWV register, taking the absolute value and comparing it
against the ISUMLVL threshold.
If
ISUM INWV ISUMLVL
(11)
it is assumed that the neutral current is equal to the sum
of the phase currents, and the system functions correctly.
If
ISUM INWV ISUMLVL
(12)
a tamper situation may have occurred, and Bit 20 (MISMTCH) in
the STATUS1 register is set to 1.
An interrupt attached to the flag can be enabled by setting Bit 20
(MISMTCH) in the MASK1 register. When enabled, the IRQ1
pin is set to low when the Status Bit MISMTCH is set to 1.
Writing to the STATUS1 register with Bit 20 (MISMTCH) set to 1
clears the status bit and returns the IRQ1 pin to high.
If ISUM INWV ISUMLVL, the MISMTCH bit = 0.
If ISUM INWV ISUMLVL, the MISMTCH bit = 1
ISUMLVL, the positive threshold used in Equation 11 and
Equation 12, is a 24-bit signed register. Because it is used in a
comparison with an absolute value, always set ISUMLVL to a
positive number from 0x00000 to 0x7FFFFF. ISUMLVL uses the
same scale as the outputs of the current ADC; therefore, writing
5,928,256 (0x5A7540) to the ISUMLVL register sets the
mismatch detection level to full scale (see the Current Channel
ADC section).
Writing 0x000000 (the default value) or a negative value to the
ISUMLVL register signifies that the MISMTCH event is always
triggered. To avoid continuously triggering MISMTCH events,
write the appropriate value for the application to the ISUMLVL
register after power-up or after a hardware or software reset.
The serial ports of the ADE7868A/ADE7878A work with 32-,
16-, or 8-bit words, whereas the DSP works with 28-bit words.
The 28-bit signed ISUM register is transmitted as a 32-bit
register with the four MSBs padded with 0s (see Figure 54).
31
28 27
0
0000
28-BIT SIGNED NUMBER
BIT 27 IS A SIGN BIT
Figure 54. ISUM[27:0] Register Transmitted as a 32-Bit Word
Like the xIGAIN registers shown in Figure 34, the ISUMLVL
register is sign extended to 28 bits and padded with four 0s for
transmission as a 32-bit register.
Rev. C | Page 38 of 96
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