ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
At the end of the peak detection period in the current channel,
Bit 23 (PKI) in the STATUS1 register is set to 1. If Bit 23 (PKI)
in the MASK1 register is set, the IRQ1 interrupt pin is driven low
at the end of PEAKCYC period and Status Bit 23 (PKI) in the
STATUS1 register is set to 1. In a similar way, at the end of the
peak detection period in the voltage channel, Bit 24 (PKV) in the
STATUS1 register is set to 1. If Bit 24 (PKV) in the MASK1
register is set, the IRQ1 interrupt pin is driven low at the end of
PEAKCYC period and Status Bit 24 (PKV) in the STATUS1
register is set to 1. To find the phase that triggered the interrupt,
one of either the IPEAK or VPEAK registers is read immediately
after reading the STATUS1 register. Next, the status bits are
cleared and the IRQ1 pin is set to high by writing to the
STATUS1 register with the status bit set to 1.
the PHSTATUS register to identify the phase that generated the
overvoltage.
Next, Bit 18 (OV) in the STATUS1 register and all Bits[11:9]
(OVPHASE[2:0]) in the PHSTATUS register are cleared. Set the
IRQ1 pin to high by writing to the STATUS1 register with the
status bit set to 1. See Figure 53 for overvoltage detection in
Phase A voltage.
PHASE A
VOLTAGE CHANNEL
OVERVOLTAGE
DETECTED
OVLVL[23:0]
Note that the internal zero-crossing counter is always active. By
setting Bits[4:2] (PEAKSEL[2:0]) in the MMODE register, the
first peak detection result is not executed across a full PEAKCYC
period. Writing to the PEAKCYC register when the PEAKSEL[2:0]
bits are set resets the zero-crossing counter, thereby ensuring
that the first peak detection result is obtained across a full
PEAKCYC period.
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF FIRST
PEAKCYC PERIOD
END OF FIRST
PEAKCYC = 16 PERIOD
END OF SECOND
PEAKCYC = 16 PERIOD
BIT 18 (OV) OF
STATUS1
BIT 9 (OVPHASE)
OF PHSTATUS
STATUS1[18] AND
PHSTATUS[9]
CANCELLED BY A
WRITE OF STATUS1
WITH OV BIT SET.
Figure 53. Overvoltage Detection, Phase A
PHASE A
CURRENT
BIT 24
OF IPEAK
BIT 24 OF IPEAK
CLEARED TO 0 AT
THE END OF SECOND
PEAKCYC PERIOD
When the absolute instantaneous value of the voltage rises
above the threshold from the OVLVL register, Bit 18 (OV) in
the STATUS1 register and Bit 9 (OVPHASE[0]) in the PHSTATUS
register are set to 1. Writing the STATUS1 register with Bit 18
(OV) set to 1 cancels Bit 18 (OV) of the STATUS1 register and
Bit 9 (OVPHASE[0]) in the PHSTATUS register. The procedure
to manage overvoltage events is as follows:
PHASE B
CURRENT
BIT 25
OF IPEAK
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF SECOND
PEAKCYC PERIOD
BIT 25 OF IPEAK
SET TO 1 AT THE
END OF SECOND
PEAKCYC PERIOD
Figure 52. Peak Level Detection
Overvoltage and Overcurrent Detection
1. Enable OV interrupts in the MASK1 register by setting
Bit 18 (OV) to 1.
2. When an overvoltage event happens, the IRQ1 interrupt
pin goes low.
3. The STATUS1 register is read with Bit 18 (OV) set to 1.
4. The PHSTATUS register is read, identifying on which
phase or phases an overvoltage event happened.
5. The STATUS1 register is written with Bit 18 (OV) set to 1,
immediately erasing Bit OV and Bits[11:9] (OVPHASE[2:0])
of the PHSTATUS register.
The ADE7854A/ADE7858A/ADE7868A/ADE7878A detect
when the instantaneous absolute value measured on the voltage
and current channels becomes greater than the thresholds set in
the OVLVL and OILVL 24-bit unsigned registers.
In case of an overcurrent event, if Bit 17 (OI) in the MASK1
register is set, the IRQ1 interrupt pin is driven low. Immediately
thereafter, Bit 17 (OI) in the STATUS1 register is set and one of
the Bits[5:3] (OIPHASE[2:0]) in the PHSTATUS register is also
Setting Bit 18 (OV) in the MASK1 register drives the IRQ1
interrupt pin low during an overvoltage event. There are two
set, which internally identifies the phase that generated the
interrupt.
status flags set when the IRQ1 interrupt pin is driven low. The
first flag is set by Bit 18 (OV) in the STATUS1 register and the
second flag is set by one of the Bits[11:9] (OVPHASE[2:0]) in
Rev. C | Page 37 of 96
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