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ADE7854AACPZ View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
ADE7854AACPZ
ADI
Analog Devices ADI
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
resolution of the ZX detection, the LPF1 cannot be disabled.
Figure 45 shows how the zero-crossing signal is detected.
To provide further protection from noise, input signals to the
voltage channel with amplitude lower than 10% of full scale do
not generate zero-crossing events at all. The Current Channel ZX
detection circuit is active for all input signals independent of their
amplitudes.
The ADE7854A/ADE7858A/ADE7868A/ADE7878A contain
six zero-crossing detection circuits, one for each phase voltage
and current channel. Each circuit drives one flag in the STATUS1
register. If a circuit placed in the Phase A voltage channel detects
one zero-crossing event, Bit 9 (ZXVA) in the STATUS1 register
is set to 1.
Similarly, the Phase B voltage circuit drives Bit 10 (ZXVB), the
Phase C voltage circuit drives Bit 11 (ZXVC), and circuits placed
in the current channel drive Bit 12 (ZXIA), Bit 13 (ZXIB), and
Bit 14 (ZXIC) in the STATUS1 register. If a ZX detection bit is
set in the MASK1 register, the IRQ1 interrupt pin is driven low
and the corresponding status flag is set to 1. The status bit is
cleared and the IRQ1 pin is set to high by writing to the STATUS1
register with the status bit set to 1.
Zero-Crossing Timeout
Every zero-crossing detection circuit has an associated timeout
register. This register is loaded with the value written into the
16-bit ZXTOUT register and is decremented (1 LSB) every
62.5 μs (16 kHz clock). Every time a zero crossing is detected,
the register resets to the ZXTOUT value. The default value of
this register is 0xFFFF. If the timeout register decrements to 0
before a zero crossing is detected, one of Bits[8:3] of the
STATUS1 register is set to 1. Bit 3 (ZXTOVA), Bit 4 (ZXTOVB),
and Bit 5 (ZXTOVC) in the STATUS1 register refer to Phase A,
Phase B, and Phase C of the voltage channel; Bit 6 (ZXTOIA),
Bit 7 (ZXTOIB), and Bit 8 (ZXTOIC) in the STATUS1 register
refer to Phase A, Phase B, and Phase C of the current channel.
Setting a ZXTOIx or ZXTOVx bit in the MASK1 register drives
the IRQ1 interrupt pin low when the corresponding status bit is set
to 1. Writing to the STATUS1 register with the status bit set to 1
clears the status bit and returns the IRQ1 pin to high.
The resolution of the ZXTOUT register is 62.5 μs (16 kHz
clock) per LSB. Thus, the maximum timeout period for an
interrupt is 4.096 sec: 216/16 kHz.
Figure 44 shows the mechanism of the zero-crossing timeout
detection when the voltage or the current signal stays at a fixed
dc level for more than 62.5 μs × ZXTOUT μs.
16-BIT INTERNAL
REGISTER VALUE
ZXTOUT
VOLTAGE
OR
CURRENT
0V
SIGNAL
ZXTOxy FLAG IN
STATUS1[31:0], x = V, I
y = A, B, C
IRQ1 INTERRUPT PIN
Figure 44. Zero-Crossing Timeout Detection
IA, IB, IC,
OR
VA, VB, VC
REFERENCE
PGA
ADC
DSP
HPFDIS
[23:0]
xIGAIN[23:0] OR
xVGAIN[23:0]
HPF
ZX
DETECTION
LPF1
1
0.855
39.6° OR 2.2ms @ 50Hz
0V ZX
ZX
ZX ZX
IA, IB, IC,
OR VA, VB, VC
LPF1 OUTPUT
Figure 45. Zero-Crossing Detection on Voltage and Current Channels
Rev. C | Page 33 of 96
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