ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
The SAGCYC register represents the number of half line cycles
that the phase voltage must remain below the level indicated in
the SAGLVL register to trigger a sag condition; 0 is not a valid
number for SAGCYC. For example, when the sag cycle
(SAGCYC[7:0]) contains 0x07, the sag flag in the STATUS1
register is set at the end of the seventh half line cycle for which
the line voltage falls below the threshold. If Bit 16 (sag) in
MASK1 is set, the IRQ1 interrupt pin is driven low during a sag
event at the same moment Status Bit 16 (sag) in the STATUS1
register is set to 1. Writing to the STATUS1 register with the
status bit set to 1 clears the sag status bit in the STATUS1 register,
clears Bits[14:12] (VSPHASE[2], VSPHASE[1], and
VSPHASE[0]) of the PHSTATUS register, and returns the IRQ1
pin to high.
When the Phase B voltage falls below the indicated threshold in
the SAGLVL register for two line cycles, Bit VSPHASE[1] in the
PHSTATUS register is set to 1 and Bit VSPHASE[0] clears to 0.
Simultaneously, Bit 16 (sag) in the STATUS1 register is set to 1 to
indicate the condition.
Note that the internal zero-crossing counter is always active. By
setting the SAGLVL register, the first sag detection result does
not execute across a full SAGCYC period. Initializing the SAGLVL
prior to writing to the SAGCYC register resets the zero-crossing
counter, thus ensuring that the first sag detection result is
obtained across a full SAGCYC period.
To manage sag events, follow these steps:
1. Enable sag interrupts in the MASK1 register by setting
Bit 16 (sag) to 1.
2. When a sag event happens and the IRQ1 interrupt pin goes
low, Bit 16 (sag) in the STATUS1 register is set to 1.
3. Read the STATUS1 register with Bit 16 (sag) set to 1.
4. Read the PHSTATUS register to identify on which phase or
phases a sag event happened.
5. Write the STATUS1 register with Bit 16 (sag) set to 1 to
immediately erase the sag bit and Bits[14:12] (VSPHASE[2],
VSPHASE[1], and VSPHASE[0]) of the PHSTATUS register.
Sag Level Set
The content of the SAGLVL[23:0] sag level register is compared
to the absolute value of the output from the HPF. Writing 5,928,256
(0x5A7540) to the SAGLVL register sets the sag detection level
at full scale (see the Voltage Channel ADC section); thus, the sag
event triggers continuously. Writing 0x00 or 0x01 sets the sag
detection level to 0; consequently, the sag event never triggers.
The serial ports of the ADE7854A/ADE7858A/ADE7868A/
ADE7878A work on 32-, 16-, or 8-bit words (see the Current
Waveform Gain Registers section). Similar to the register shown
in Figure 37, the SAGLVL register is accessed as a 32-bit register
with eight MSBs padded with 0s.
Peak Detection
The ADE7854A/ADE7858A/ADE7868A/ADE7878A record the
maximum absolute values reached by the voltage and current
channels over a certain number of half line cycles and store
them into the least significant 24 bits of the VPEAK and IPEAK
32-bit registers.
The PEAKCYC register contains the number of half line cycles
used as a time base for the measurement. The circuit uses the zero-
crossing points identified by the zero-crossing detection circuit.
Bits[4:2] (PEAKSEL[2:0]) in the MMODE register select the
phases upon which the peak measurement is performed. Bit 2
selects Phase A, Bit 3 selects Phase B, and Bit 4 selects Phase C.
Selecting more than one phase to monitor the peak values pro-
portionally decreases the measurement period indicated in the
PEAKCYC register because zero crossings from more phases are
involved in the process.
When a new peak value is determined, one of the Bits[26:24]
(IPPHASE[2:0] or VPPHASE[2:0]) in the IPEAK and VPEAK
registers is set to 1, identifying the phase that triggered the peak
detection event. For example, if a peak value is identified on
Phase A current, Bit 24 (IPPHASE[0]) in the IPEAK register is
set to 1. If the next time, a new peak value is measured on
Phase B, Bit 24 (IPPHASE[0]) of the IPEAK register is cleared
to 0, and Bit 25 (IPPHASE[1]) of the IPEAK register is set to 1.
Figure 51 shows the composition of the IPEAK and VPEAK
registers.
IPPHASE/VPPHASE BITS
31
27 26 25 24 23
0
00000
24 BIT UNSIGNED NUMBER
PEAK DETECTED
ON PHASE C
PEAK DETECTED
ON PHASE A
PEAK DETECTED
ON PHASE B
Figure 51. Composition of IPEAK[31:0] and VPEAK[31:0] Registers
Figure 52 shows how the ADE7854A, ADE7858A, ADE7868A,
and ADE7878A record the peak value on the current channel
when measurements on Phase A and Phase B are enabled (the
PEAKSEL[2:0] bits in the MMODE register are 011). The
PEAKCYC register is set to 16, meaning that the peak
measurement cycle is four line periods.
The maximum absolute value of Phase A is the greatest during the
first four line periods (PEAKCYC = 16); therefore, the maximum
absolute value is written into the least significant 24 bits of the
IPEAK register, and Bit 24 (IPPHASE[0]) of the IPEAK register
is set to 1 at the end of the period. This bit remains at 1 for the
duration of the second PEAKCYC period of four line cycles.
The maximum absolute value of Phase B is the greatest during
the second PEAKCYC period; therefore, the maximum absolute
value is written into the least significant 24 bits of the IPEAK
register, and Bit 25 (IPPHASE[1]) in the IPEAK register is set to
1 at the end of the period.
Rev. C | Page 36 of 96
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