ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
Phase Sequence Detection
The ADE7854A/ADE7858A/ADE7868A/ADE7878A have
on-chip phase sequence error detection circuits. This detection
works on phase voltages and considers only the zero crossings
determined by their negative to positive transitions.
The regular succession of these zero-crossing events is Phase A
followed by Phase B followed by Phase C (see Figure 47). If the
sequence of zero-crossing events is, instead, Phase A followed by
Phase C followed by Phase B, then Bit 19 (SEQERR) in the
STATUS1 register is set.
Setting Bit 19 (SEQERR) in the MASK1 register to 1 and triggering
a phase sequence error event drives the IRQ1 interrupt pin low.
Writing to the STATUS1 register with Bit 19 (SEQERR) set to 1
clears the status bit and sets the IRQ1 pin to high.
The phase sequence error detection circuit is functional only
when the device is connected in a 3-phase, 4-wire, three-voltage
sensor configuration (Bits[5:4], CONSEL[1:0] in the ACCMODE
register, set to 00). In all other configurations, only two voltage
sensors are used; therefore, do not use the detection circuit in
these cases. Instead, use the time intervals between phase voltages
to analyze the phase sequence (see the Time Interval Between
Phases section).
Figure 46 presents the case in which Phase A voltage is not followed
by Phase B voltage; rather, Phase A voltage is followed by Phase C
voltage. Each time a negative to positive zero crossing occurs,
Bit 19 (SEQERR) in the STATUS1 register is set to 1 because zero
crossings on Phase C, Phase B, or Phase A cannot follow zero
crossings from Phase A, Phase C, or Phase B, respectively.
PHASE A
PHASE C
PHASE B
A, B, C PHASE
VOLTAGES AFTER
LPF1
Changing the Phase Voltage Datapath section for more
information.
Time Interval Between Phases
The ADE7854A/ADE7858A/ADE7868A/ADE7878A are
capable of measuring the time delay between phase voltages,
between phase currents, or between voltages and currents of the
same phase. The negative to positive transitions identified by the
zero-crossing detection circuit serve as start and stop measuring
points. Only one set of such measurements is available at one time
based on Bits[10:9] (ANGLESEL[1:0]) in the COMPMODE
register.
PHASE A
PHASE B
PHASE C
ZX A
ZX B
ZX C
Figure 47. Regular Succession of Phase A, Phase B, and Phase C
Delays Between Voltages and Currents
To measure the delays between voltages and currents on the same
phase, set the ANGLESEL[1:0] bits to 00, the default value. The
delay between Phase A voltage and Phase A current is stored in
the 16-bit unsigned ANGLE0 register (see Figure 48). In a similar
way, the delays between voltages and currents on Phase B and
Phase C are stored in the ANGLE1 and ANGLE2 registers,
respectively.
PHASE A
VOLTAGE
PHASE A
CURRENT
ZX A
ZX C
ZX B
BIT 19 (SEQERR) IN
STATUS1 REGISTER
IRQ1
STATUS1[19] SET TO 1
STATUS1[19] CANCELLED
BY A WRITE TO THE
STATUS1 REGISTER WITH
SEQERR BIT SET
Figure 46. SEQERR Bit Set to 1 When Phase A Voltage Is Followed by
Phase C Voltage
ANGLE0
Figure 48. Delay Between Phase A Voltage and Phase A Current Is
Stored in the ANGLE0 Register
Delays Between Phase Voltages
To measure the delays between phase voltages, set the
ANGLESEL[1:0] bits to 01. The delay between the Phase A voltage
and the Phase C voltage is stored in the ANGLE0 register. The
delay between Phase B voltage and Phase C voltage is stored in
the ANGLE1 register, and the delay between Phase A voltage
and Phase B voltage is stored in the ANGLE2 register (see
Figure 49).
When a phase sequence error is detected, the time measurement
between various phase voltages (see the Time Interval Between
Phases section) can help to identify which phase voltage is to be
considered with another phase current in the computational
datapath. Use Bits[9:8] (VTOIA[1:0]), Bits[11:10] (VTOIB[1:0]),
and Bits[13:12] (VTOIC[1:0]) in the CONFIG register to direct
one phase voltage to the datapath of another phase. See the
Rev. C | Page 34 of 96
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