ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
PHASE A
PHASE B
PHASE C
ANGLE2
ANGLE1
ANGLE0
Figure 49. Delays Between Phase Voltages (Currents)
Delays Between Phase Currents
To measure the delays between phase currents, set the ANGLE-
SEL[1:0] bits to 10. Similar to delays between phase voltages, the
delay between Phase A and Phase C currents is stored into the
ANGLE0 register, the delay between Phase B and Phase C currents
is stored in the ANGLE1 register, and the delay between Phase A
and Phase B currents is stored into the ANGLE2 register (see
Figure 49).
Power Factor
The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit
unsigned registers with 1 LSB corresponding to 3.90625 μs
(256 kHz clock), which means a resolution of 0.0703° (360° ×
50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × 60 Hz/
256 kHz) for 60 Hz systems. The delays between phase voltages
or phase currents characterize the balance of the load. The delays
between phase voltages and currents are used to compute the
power factor on each phase, as shown in Equation 5.
cosφx
=
cos
ANGLEx
360
f LINE
(5)
256 kHz
where fLINE = 50 Hz or 60 Hz.
Period Measurement
The ADE7854A/ADE7858A/ADE7868A/ADE7878A provide
the period measurement of the line in the voltage channel. Bits[1:0]
(PERSEL[1:0]) in the MMODE register select the phase voltage
that is used for this measurement. The period register is a 16-bit
unsigned register that updates every line period. Because of the
LPF1 filter (see Figure 45), a settling time of 30 ms to 40 ms is
associated with this filter before the measurement is stable.
The period measurement has a resolution of 3.90625 μs/LSB
(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)
when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)
when the line frequency is 60 Hz. The value of the period register
for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and
for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The
length of the register enables the measurement of line frequencies
as low as 3.9 Hz (256 kHz/216). The period register is stable at
±1 LSB when the line is established and the measurement does
not change.
The following expressions can be used to compute the line
period and frequency using the period register:
TL
PERIOD[15: 0]
256 103
1 sec
(6)
fL
256 103
PERIOD[15:0]
1[Hz]
(7)
Phase Voltage Sag Detection
The ADE7854A/ADE7858A/ADE7868A/ADE7878A can be
programmed to detect when the absolute value of any phase
voltage drops below a certain peak value for a number of half
line cycles.
The phase where this event takes place is identified in Bits[14:12]
(VSPHASE[x]) of the PHSTATUS register. See Figure 50 for an
example of this condition.
Figure 50 shows Phase A voltage falling below a threshold that
is set in the sag level register (SAGLVL) for four half line cycles
(SAGCYC = 4). When Bit 16 (sag) in the STATUS1 register is set to
1 to indicate the condition, Bit VSPHASE[0] in the PHSTATUS
register is also set to 1 because the event happened on Phase A. All
Bits[14:12] (VSPHASE[2], VSPHASE[1], and VSPHASE[0]) of the
PHSTATUS register (not just the VSPHASE[0] bit) are erased by
writing to the STATUS1 register with the sag bit set to 1.
FULL SCALE
SAGLVL[23:0]
PHASE B VOLTAGE
FULL SCALE
SAGLVL[23:0]
SAGCYC[7:0] = 0x4
PHASE A VOLTAGE
SAGCYC[7:0] = 0x4
BIT 16 (SAG) IN
STATUS1[31:0]
STATUS1[16] AND
PHSTATUS[12]
CANCELLED BY A
WRITE TO
STATUS1[31:0]
WITH SAG BIT SET
IRQ1 PIN
VSPHASE[0] =
PHSTATUS[12]
VSPHASE[1] =
PHSTATUS[13]
STATUS1[16] AND
PHSTATUS[13]
SET TO 1
Figure 50. Sag Detection
Rev. C | Page 35 of 96
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