ADE7854AACPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADE7854AACPZ' PDF : 96 Pages View PDF
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Data Sheet
PHASE COMPENSATION
As described in the Current Channel ADC and Voltage Channel
ADC sections, the datapath for both current and voltages is the
same. The phase error between current and voltage signals intro-
duced by the ADE7854A/ADE7858A/ADE7868A/ADE7878A is
negligible. However, the ADE7854A/ADE7858A/ADE7868A/
ADE7878A must work with transducers that may have inherent
phase errors. For example, a current transformer (CT) with a
phase error of 0.1° to 3° is common. These phase errors can
vary from device to device, and they must be corrected to
perform accurate power calculations.
The errors associated with phase mismatch are particularly
noticeable at low power factors. The phase calibration registers
digitally calibrate these small phase errors. To compensate for
the small phase errors, a small time delay or time advance is
introduced into the signal processing chain of the device.
The phase calibration registers (APHCAL, BPHCAL, and
CPHCAL) are 10-bit registers that can vary the time advance
in the voltage channel signal path from −374.0 μs to +61.5 μs.
Negative values written to the xPHCAL registers represent a
time advance, whereas positive values represent a time delay. One
LSB is equivalent to 0.976 μs of time delay or time advance (at a
clock rate of 1.024 MHz). At a line frequency of 60 Hz, this gives
a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the
fundamental. This corresponds to a total correction range of
−8.079° to +1.329° at 60 Hz. At 50 Hz, the correction range is
−6.732° to +1.107° and the resolution is 0.0176° (360° × 50 Hz/
1.024 MHz).
Given a phase error of x degrees, measured using the phase
voltage as the reference, the corresponding LSBs are computed
by dividing x by the phase resolution (0.0211°/LSB for 60 Hz
and 0.0176°/LSB for 50 Hz). Results between −383 and +63 are
the only acceptable values; numbers outside this range are not
accepted. When the current leads the voltage, the result is
negative and the absolute value is written into the xPHCAL
registers. When the current lags the voltage, the result is positive
and 512 is added to the result before writing it into xPHCAL.
APHCAL, BPHCAL, or CHPCAL =
(13)
PHASE
_
x
RESOLUTION
,
x
0
x
PHASE _ RESOLUTION
512,
x
0
Figure 57 shows the use of phase compensation to remove an
x = −1° phase lead in the IA current channel from the external
current transducer (equivalent of 55.5 μs for 50 Hz systems). To
cancel the lead (1°) in the current channel of Phase A, introduce
a phase lead into the corresponding voltage channel. Using
Equation 13, APHCAL is 57 LSBs, rounded up from 56.8. To
achieve the phase lead, introduce a time delay of 55.73 μs into
the Phase A current.
The serial ports of the device work with 32-, 16-, or 8-bit words,
whereas the DSP works with 28-bit words. As shown in Figure 56,
the 10-bit APHCAL, BPHCAL, and CPHCAL registers are
accessed as 16-bit registers with the six MSBs padded with 0s.
15
10 9
0
0000 00
xPHCAL
Figure 56. xPHCAL Registers Transmitted as 16-Bit Registers
IAP
IA
IAN
PGA1
VAP
VA
VN
PGA3
ADC
PHASE
CALIBRATION
APHCAL = 57
ADC
1°
IA
VA
IA
PHASE COMPENSATION
ACHIEVED DELAYING
IA BY 56µs
VA
50Hz
Figure 57. Phase Calibration on Voltage Channels
Rev. C | Page 40 of 96
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