ADSP-21160M/ADSP-21160N
Table 28. Link Ports—Transmit
Parameter
Min
Timing Requirements
tSLACH
LACK Setup Before LCLK High
14
tHLACH
LACK Hold After LCLK High
–2
Switching Characteristics
tDLDCH
tHLDCH
tLCLKTWL
tLCLKTWH
tDLACLK
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low1
LCLK Width High2
LCLK Low Delay After LACK High3
–2
0.5tLCLK – 0.5
0.5tLCLK – 0.5
0.5tLCLK + 4
1 For ADSP-21160M, specification is 0.5tLCLK–1.5 ns (minimum) and 0.5tLCLK+1.5 ns (maximum).
2 For ADSP-21160M, specification is 0.5tLCLK–1.5 ns (minimum) and 0.5tLCLK+1.5 ns (maximum).
3 For ADSP-21160M, specification is 0.5tLCLK+5 ns (minimum) and 3tLCLK+11 ns (maximum).
Max
4
0.5tLCLK + 0.5
0.5tLCLK + 0.5
3/2tLCLK + 11
Unit
ns
ns
ns
ns
ns
ns
ns
LCLK
LDAT(7:0)
LACK (IN)
TRANSMIT
tLCLKTWH
tLCLKTWL
tHLDCH
tDLDCH
OUT
LAST NIBBLE/BYTE
TRANSMITTED
FIRST NIBBLE/BYTE
TRANSMITTED
LCLK INACTIVE
(HIGH)
tSLA CH
tHLAC H
tDLACLK
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE/BYTE TRANSMITTED.
Figure 25. Link Ports—Transmit
Rev. C | Page 42 of 60 | February 2013