ADSP-21160M View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21160M' PDF : 52 Pages View PDF
ADSP-21160M/ADSP-21160N
JTAG Test Access Port and Emulation
For JTAG Test Access Port and emulation, see Table 36 and
Figure 28.
Table 36. JTAG Test Access Port and Emulation
Parameter
Timing Requirements
tTCK
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1
TRST Pulsewidth
Min
Max
Unit
tCK
ns
5
ns
6
ns
7
ns
18
ns
4 tCK
ns
Switching Characteristics
tDTDO
tDSYS
TDO Delay from TCK Low
System Outputs Delay After TCK Low2
13
ns
30
ns
1 System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, PA, BRST, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, and RESET.
2 System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP,
DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, and BMS.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP
tD TDO
tDSYS
tHTAP
tSSYS
Figure 28. JTAG Test Access Port and Emulation
tHSYS
Rev. C | Page 46 of 60 | February 2013
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