ADSP-21160M/ADSP-21160N
Table 35. Serial Ports—External Late Frame Sync
Parameter
Min
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1,
MFD = 01
tDDTENFS
Data Enable from Late FS or MCE = 1, MFD = 01
1.0
1 MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.
Max
Unit
13
ns
ns
RCLK
DATA RECEIVE— INTERNAL CLOCK
DRIVE
EDGE
tSCLKIW
SAMPLE
EDGE
tHOFSE
RFS
tDFSE
tSFSI
tSDRI
tHFSI
tHDRI
DATA RECEIVE— EXTERNAL CLOCK
DRIVE
EDGE
tSCLKW
SAMPLE
EDGE
RCLK
tHOFSE
tDFSE
tSFSE
tHFSE
RFS
tSDRE
tHDRE
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT— INTERNAL CLOCK
DRIVE
EDGE
tSCLKIW
SAMPLE
EDGE
TCLK
tHOFSI
tDFSI
tSFSI
TFS
tHDTI
tDDTI
DT
tHFSI
DATA TRANSMIT— EXTERNAL CLOCK
DRIVE
EDGE
tSCLKW
SAMPLE
EDGE
TCLK
tHOFSE
tDFSE
tSFSE
tHFSE
TFS
tHDTE
tDDTE
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
TCLK
(EXT)
DT
TCLK
(INT)
tDDTEN
DRIVE
EDGE
tDDTIN
TCLK /
RCLK
TCLK /
RCLK
tDD TT E
DRIVE
EDGE
tDDTTI
DT
Figure 27. Serial Ports
Rev. C | Page 45 of 60 | February 2013