Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the output enable/disable diagram (Figure 31). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ï„V
to be the difference between the ADSP-21160x DSP’s output
voltage and the input threshold for the device requiring the hold
time. A typical ï„V will be 0.4 V. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tDATRWH for the write cycle).
TO
OUTPUT
PIN
506
1.5V
30pF
Figure 32. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
INPUT
OR
OUTPUT
1.5V
1.5V
Figure 33. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
ADSP-21160M/ADSP-21160N
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 32). Figure 34, Figure 35, Figure 37,
and Figure 38 show how output rise time varies with capaci-
tance. Figure 36 and Figure 39 graphically show how output
delays and holds vary with load capacitance. (Note that this
graph or derating does not apply to output disable delays; see
Output Disable Time on Page 48.) The graphs of Figure 34
through Figure 39 may not be linear outside the ranges shown.
30
25
RISE TIME
20
Y = 0.086687X + 2.18
15
FALL TIME
10
Y = 0.072781X + 1.99
5
0
0
50
100
150
200
LOAD CAPACITANCE – pF
Figure 34. ADSP-21160M Typical Output Rise Time (10%–90%, VDDEXT = Max)
vs. Load Capacitance
25
20
RISE TIME
Y = 0.0813x + 2.312
15
TBD
FALL TIME
10
Y = 0.0834x + 1.0653
5
0
0
50
100
150
200
250
LOAD CAPACITANCE – pF
Figure 35. ADSP-21160M Typical Output Rise Time (10%–90%, VDDEXT = Min)
vs. Load Capacitance
Rev. C | Page 49 of 60 | February 2013