ADSP-21160M/ADSP-21160N
Table 37. ADSP-21160x Operation Types vs. Input Current
Operation
Peak Activity1
High Activity1
Low Activity1
Instruction Type
Multifunction
Multifunction
Single Function
Instruction Fetch
Core Memory Access2
Cache
2 per tCK Cycle
(DM Ø‹ 64 and PM Ø‹ 64)
Internal Memory
1 per tCK Cycle
(DM Ø‹ 64)
Internal Memory
None
Internal Memory DMA
External Memory DMA
1 per 2 tCCLK Cycles
1 per External Port Cycle (؋64)
1 per 2 tCCLK Cycles
1 per External Port Cycle (Ø‹ 64)
None
None
Data Bit Pattern for Core
Worst Case
Random
N/A
Memory Access and DMA
1 Peak activity = IDD-INPEAK, high activity = IDD-INHIGH, and low activity = IDD-INLOW. The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.
2 These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on page 20.
Table 38. External Power Calculations (ADSP-21160N Example)
Pin Type
Address
MS0
WRx
Data
CLKOUT
No. of Pins
15
1
2
64
1
% Switching
50
0
50
×C
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
×f
× 24 MHz
× 24 MHz
× 24 MHz
× 24 MHz
× 48 MHz
PEXT
× VDD2
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
= PEXT
= 0.088 W
= 0.000 W
= 0.023 W
= 0.123 W
= 0.003 W
= 0.237 W
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
TEST CONDITIONS
The test conditions for timing parameters appearing in
ADSP-21160x specifications on page 17 include output disable
time, output enable time, and capacitive loading.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high-impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ï„V is dependent on the capacitive load, CL and
the load current, IL. This decay time can be approximated by the
following equation:
tDECAY = (CLï„V)/IL
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 31. The time tMEASURED is the inter-
val from when the reference signal switches to when the output
voltage decaysï€ ï„V from the measured output high or output low
voltage. tDECAY is calculated with test loads CL and IL, and with
ï„V equal to 0.5 V.
REFERENCE
SIGNAL
tDIS
VOH (MEASURED)
VOL (MEASURED)
tMEASURED
tENA
VOH (MEASURED) – $V 2.0V
VOL (MEASURED) + $V 1.0V
tDECAY
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
Figure 31. Output Enable/Disable
Rev. C | Page 48 of 60 | February 2013