Serial Ports
For serial ports, see Table 29, Table 30, Table 31, Table 32,
Table 33, Table 34, Table 35, Figure 26, and Figure 27. To deter-
mine whether communication is possible between two devices
Table 29. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE
tHFSE
tSDRE
tHDRE
tSCLKW
tSCLK
TFS/RFS Setup Before TCLK/RCLK1
TFS/RFS Hold After TCLK/RCLK1
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1, 2
TCLK/RCLK Width3
TCLK/RCLK Period
1 Referenced to sample edge.
2 For ADSP-21160M, specification is 4 ns, minimum.
3 For ADSP-21160M, specification is 14 ns, minimum.
Table 30. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI
TFS Setup Before TCLK1; RFS Setup Before RCLK1
tHFSI
TFS/RFS Hold After TCLK/RCLK1, 2
tSDRI
Receive Data Setup Before RCLK1
tHDRI
Receive Data Hold After RCLK1
1 Referenced to sample edge.
2 For ADSP-21160M, specification is 1 ns, minimum.
Table 31. Serial Ports—External or Internal Clock
Parameter
Switching Characteristics
tDFSE
tHOFSE
RFS Delay After RCLK (Internally Generated RFS)1
RFS Hold After RCLK (Internally Generated RFS)1
1 Referenced to drive edge.
Table 32. Serial Ports—External Clock
Parameter
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFS Delay After TCLK (Internally Generated TFS)1
TFS Hold After TCLK (Internally Generated TFS)1
Transmit Data Delay After TCLK1
Transmit Data Hold After TCLK1
1 Referenced to drive edge.
ADSP-21160M/ADSP-21160N
at clock speed n, the following specifications must be confirmed:
1) frame sync delay and frame sync setup and hold, 2) data delay
and data setup and hold, and 3) SCLK width.
Min
3.5
4
1.5
6.5
8
2tCCLK
Max
Unit
ns
ns
ns
ns
ns
ns
Min
8
tCCLK/2 + 1
6.5
3
Max
Unit
ns
ns
ns
ns
Min
Max
Unit
13
ns
3
ns
Min
Max
Unit
13
ns
3
ns
16
ns
0
ns
Rev. C | Page 43 of 60 | February 2013