ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
ADSP-21371/ADSP-21375
DAI_P20–1
(SCLK)
DAI_P20–1
(FRAME SYNC)
DAI_P20–1
(DATA CHANNEL
A/B)
DRIVE
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
SAMPLE
DRIVE
tSFSE/I
tHFSE/I
tDDTENFS
tDDTLFSE
tHDTE/I
1ST BIT
tDDTE/I
2ND BIT
LATE EXTERNAL TRANSMIT FS
DAI_P20–1
(SCLK)
DAI_P20–1
(FRAME SYNC)
DRIVE
SAMPLE
DRIVE
tSFSE/I
tHFSE/I
DAI_P20–1
(DATA CHANNEL
A/B)
tDDTENFS
tHDTE/I
1ST BIT
tDDTE/I
2ND BIT
tDDTLFSE
NOTES
1. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20–1 PINS.
THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND
FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU.
Figure 20. External Late Frame Sync1
1 This figure reflects changes made to support left-justified sample pair mode.
Rev. C | Page 32 of 52 | September 2009
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