ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
ADSP-21371/ADSP-21375
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 31. IDP
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 31. Input Data Port (IDP)
1.2 V, 266 MHz
Parameter
Min
Max
Unit
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge
3.8
ns
tSIHFS1
Frame Sync Hold After Serial Clock Rising Edge
2.5
ns
tSISD1
Data Setup Before Serial Clock Rising Edge
2.5
ns
tSIHD1
Data Hold After Serial Clock Rising Edge
2.5
ns
tIDPCLKW
Clock Width
(tPCLK × 4) ÷ 2 – 1
ns
tIDPCLK
Clock Period
tPCLK × 4
ns
1 The data, serial clock, and frame sync signals can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either
CLKIN or any of the DAI pins.
DAI_P20–1
(SERIAL CLOCK)
DAI_P20–1
(FRAME SYNC)
DAI_P20–1
(DATA)
SAMPLE EDGE
tIPDCLKW
tIPDCLK
tSISFS
tSIHFS
tSISD
tSIHD
Figure 22. IDP Master Timing
Rev. C | Page 34 of 52 | September 2009
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