ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADSP-21371KSWZ-2A2

SHARC Processor

Analog Devices 

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ADSP-21371/ADSP-21375

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE

tSCLKIW

SAMPLE EDGE

DAI_P20–1

(SCLK)

tHOFSIR

DAI_P20–1

(FRAME SYNC)

tDFSIR

DAI_P20–1

(DATA

CHANNEL A/B)

tSFSI

tSDRI

tHFSI

tHDRI

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE

tSCLKW

SAMPLE EDGE

DAI_P20–1

(SCLK)

tHOFSE

DAI_P20–1

(FRAME SYNC)

tDFSE

DAI_P20–1

(DATA

CHANNEL A/B)

tSFSE

tSDRE

tHFSE

tHDRE

NOTES

1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE

tSCLKIW

SAMPLE EDGE

DAI_P20–1

(SCLK)

tHOFSI

DAI_P20–1

(SCLK)

tHDTI

DAI_P20–1

(DATA

CHANNEL A/B)

tDFSI

tSFSI

tDDTI

tHFSI

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE

tSCLKW

SAMPLE EDGE

DAI_P20–1

(SCLK)

tHOFSE

DAI_P20–1

(FRAME SYNC)

tHDTE

DAI_P20–1

(DATA

CHANNEL A/B)

tDFSE

tSFSE

tDDTE

tHFSE

NOTES

1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

DAI_P20–1

(FRAME SYNC)

tDDTEN

DRIVE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

tDDTIN

SCLK

DRIVE EDGE

tDDTTE

Figure 21. Serial Ports

Rev. C | Page 33 of 52 | September 2009

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