ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
ADSP-21371/ADSP-21375
SPI Interface—Master
The processor contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 37 and Table 38 applies to both.
Table 37. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Timing Requirements
tSSPIDM
Data Input Valid To SPICLK Edge (Data Input Setup Time)
tHSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid
Switching Characteristics
tSPICLKM
tSPICHM
tSPICLM
tDDSPIDM
tHDSPIDM
tSDSCIM
tHDSM
tSPITDM
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI device select) Low to First SPICLK Edge
Last SPICLK Edge to FLAG3–0IN High
Sequential Transfer Delay
Min
8.2
2
8 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 1
Max
2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FLAG3–0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
MOSI
(OUTPUT)
CPHASE = 1
MISO
(INPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tDDSPIDM
MSB
tSSPIDM
tHSPIDM
MSB
VALID
MOSI
(OUTPUT)
CPHASE = 0
tSSPIDM
MSB
tHSPIDM
MISO
(INPUT)
MSB VALID
tDDSPIDM
tSPICLKM
tHDSM
tSPITDM
tHDSPIDM
LSB
tSSPIDM
tHSPIDM
LSB VALID
tHDSPIDM
LSB
LSB VALID
Figure 30. SPI Master Timing
Rev. C | Page 40 of 52 | September 2009
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