ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
S/PDIF Transmitter
For the ADSP-21371, serial data input to the S/PDIF transmitter
can be formatted as left-justified, I2S, or right-justified with
word widths of 16-, 18-, 20-, or 24-bits. The following sections
provide timing for the transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 25 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is delayed 12-bit clock peri-
ods (in 20-bit output mode) or 16-bit clock periods (in 16-bit
ADSP-21371/ADSP-21375
output mode) from an LRCLK transition, so that when there are
64 serial clock periods per LRCLK period, the LSB of the data
will be right-justified to the next LRCLK transition.
S/PDIF transmitter information does not apply to the
ADSP-21375.
Figure 26 shows the default I2S-justified mode. LRCLK is low
for the left channel and high for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to an
LRCLK transition but with a single serial clock period delay.
Figure 27 shows the left-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to an LRCLK
transition with no MSB delay.
DAI_P20–1
LRCLK
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LSB
LEFT CHANNEL
RIGHT CHANNEL
MSB – 2
MSB
MSB – 1
LSB + 1
LSB
LSB + 2
Figure 25. Right-Justified Mode
MSB – 2
MSB
MSB – 1
LSB + 1
LSB
LSB + 2
DAI_P20–1
LRCLK
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB – 2
MSB
MSB – 1
LSB + 1
LSB
LSB + 2
MSB – 2
MSB
MSB – 1
LSB + 1
LSB
LSB + 2
Figure 26. I2S-Justified Mode
DAI_P20–1
LRCLK
DAI_P20–1
SCLK
DAI_P20–1
SDATA
MSB – 2
MSB
MSB – 1
LEFT CHANNEL
RIGHT CHANNEL
LSB + 1
LSB
LSB + 2
MSB – 2
MSB
MSB – 1
Figure 27. Left-Justified Mode
LSB + 1
LSB
LSB + 2
MSB
MSB
MSB + 1
Rev. C | Page 37 of 52 | September 2009
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