ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
S/PDIF Receiver
For the ADSP-21371, the following section describes timing as it
relates to the S/PDIF receiver.
Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter
Switching Characteristics
tDFSI
LRCLK Delay After Serial Clock
tHOFSI
LRCLK Hold After Serial Clock
tDDTI
Transmit Data Delay After Serial Clock
tHDTI
tSCLKIW1
Transmit Data Hold After Serial Clock
Transmit Serial Clock Width
1 Serial lock frequency is 64 × Frame Sync where FS = the frequency of LRCLK.
ADSP-21371/ADSP-21375
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × Frame Sync clock. The S/PDIF
receiver information does not apply to the ADSP-21375.
1.2 V, 266 MHz
Min
Max
Unit
5
ns
–2
ns
5
ns
–2
ns
38.5
ns
DRIVE EDGE
DAI_P20–1
(SERIAL CLOCK)
DAI_P20–1
(FRAME SYNC)
DAI_P20–1
(DATA CHANNEL
A/B)
tDFSI
tHOFSI
tDDTI
tHDTI
tSCLKIW
SAMPLE EDGE
Figure 29. S/PDIF Receiver Internal Digital PLL Mode Timing
Rev. C | Page 39 of 52 | September 2009
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