ADSP-21371KSWZ-2A2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21371KSWZ-2A2' PDF : 52 Pages View PDF
ADSP-21371/ADSP-21375
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 32. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-2137x SHARC Processor Hardware
Reference.
Note that the 20-bits of external PDAP data can be provided
through the external port DATA31–12 pins. On the
ADSP-21375 processors, PDAP can not be multiplexed on the
external port (since only DATA15–0). Use the SRU DAI
instead.
Table 32. Parallel Data Acquisition Port (PDAP)
Parameter
Min
Timing Requirements
tSPCLKEN1
tHPCLKEN1
tPDSD1
tPDHD1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge
PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge
tPDCLKW
Clock Width
tPDCLK
Clock Period
Switching Characteristics
2.5
2.5
3.85
2.5
(tPCLK × 4) ÷ 2 – 3
tPCLK × 4
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × tPCLK + 3
tPDSTRIB
PDAP Strobe Pulse Width
2 × tPCLK – 1
1 Data source pins are DATA31–12 or DAI pins. Source pins for serial clock and frame sync are: 1) DATA11–10 pins, 2) DAI pins
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
DAI_P20–1
(PDAP_CLK)
DAI_P20–1
(PDAP_CLKEN)
DATA
DAI_P20–1
(PDAP_STROBE)
SAMPLE EDGE
tPDCLKW
tSPCLKEN
tPDSD
tPDCLK
tHPCLKEN
tPDHD
tPDHLDD
Figure 23. PDAP Timing
tPDSTRB
Rev. C | Page 35 of 52 | September 2009
Share Link: 
