ADSP-21477/ADSP-21478/ADSP-21479
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left-justified, I2S, or right-justified with word widths of 16, 18,
20, or 24 bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 31 shows the right-justified mode. Frame sync is high for
the left channel and low for the right channel. Data is valid on
the rising edge of serial clock. The MSB is delayed the minimum
Table 44. S/PDIF Transmitter Right-Justified Mode
Parameter
Timing Requirement
tRJD
FS to MSB Delay in Right-Justified Mode
16-Bit Word Mode
18-Bit Word Mode
20-Bit Word Mode
24-Bit Word Mode
in 24-bit output mode or the maximum in 16-bit output mode
from a frame sync transition, so that when there are 64 serial
clock periods per frame sync period, the LSB of the data is right-
justified to the next frame sync transition.
Figure 32 shows the default I2S-justified mode. The frame sync
is low for the left channel and high for the right channel. Data is
valid on the rising edge of serial clock. The MSB is left-justified
to the frame sync transition but with a delay.
Nominal
Unit
16
SCLK
14
SCLK
12
SCLK
8
SCLK
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LSB
tRJD
LEFT/RIGHT CHANNEL
MSB MSB–1 MSB–2
Figure 31. Right-Justified Mode
Table 45. S/PDIF Transmitter I2S Mode
Parameter
Timing Requirement
tI2SD
FS to MSB Delay in I2S Mode
LSB+2 LSB+1 LSB
Nominal
1
Unit
SCLK
DAI_P20–1
FS
LEFT/RIGHT CHANNEL
DAI_P20–1
SCLK
DAI_P20–1
SDATA
tI2SD
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
Figure 32. I2S-Justified Mode
Figure 33 shows the left-justified mode. The frame sync is high
for the left channel and low for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to the
frame sync transition with no delay.
Rev. C | Page 52 of 76 | July 2013