ADSP-21477 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADSP-21477

High Performance Fourth Generation DSP

Analog Devices 

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ADSP-21477/ADSP-21478/ADSP-21479

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 49. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter

Switching Characteristics

tDFSI

tHOFSI

tDDTI

tHDTI

tSCLKIW1

FS Delay After Serial Clock

FS Hold After Serial Clock

Transmit Data Delay After Serial Clock

Transmit Data Hold After Serial Clock

Transmit Serial Clock Width

1 The serial clock frequency is 64 × frame sync (FS) where FS = the frequency of LRCLK.

Min

Max

Unit

5

ns

–2

ns

5

ns

–2

ns

38.5

ns

DRIVE EDGE

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

tDFSI

tHOFSI

tDDTI

tHDTI

tSCLKIW

SAMPLE EDGE

Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. C | Page 55 of 76 | July 2013

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