ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
Media Local Bus
All the numbers given are applicable for all speed modes
(1024 FS, 512 FS, and 256 FS for 3-pin; 512 FS and 256 FS for
5-pin) unless otherwise specified. Please refer to MediaLB speci-
fication document rev 3.0 for more details.
Table 52. MLB Interface, 3-Pin Specifications
Parameter
Min
Typ
Max
Unit
3-Pin Characteristics
tMLBCLK
MLB Clock Period
1024 FS
512 FS
256 FS
20.3
ns
40
ns
81
ns
tMCKL
MLBCLK Low Time
1024 FS
6.1
ns
512 FS
14
ns
256 FS
30
ns
tMCKH
MLBCLK High Time
1024 FS
9.3
ns
512 FS
14
ns
256 FS
30
ns
tMCKR
MLBCLK Rise Time (VIL to VIH)
1024 FS
512 FS/256 FS
1
ns
3
ns
tMCKF
tMPWV1
MLBCLK Fall Time (VIH to VIL)
1024 FS
512 FS/256 FS
MLBCLK Pulse Width Variation
1024 FS
512 FS/256
1
ns
3
ns
0.7
ns p-p
2.0
ns p-p
tDSMCF
tDHMCF
tMCFDZ
tMCDRV
tMDZH2
DAT/SIG Input Setup Time
1
DAT/SIG Input Hold Time
1.2
DAT/SIG Output Time to Three-State
0
DAT/SIG Output Data Delay From MLBCLK Rising Edge
Bus Hold Time
1024 FS
2
512 FS/256
4
ns
ns
15
ns
8
ns
ns
ns
CMLB
DAT/SIG Pin Load
1024 FS
512 FS/256
40
pf
60
pf
1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (p-p).
2 The board must be designed to ensure that the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be
minimized while meeting the maximum capacitive load listed.
Rev. C | Page 58 of 76 | July 2013
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